# US 12,119,341 B2 · Electrostatic discharge diode having dielectric isolation layer

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- Number: US 12,119,341 B2
- Document ID: US12119341B2
- Status: Granted
- Kind: B2
- Application number: 17/485,961
- Filed: 2021-09-27
- Published: 2023-04-13
- Granted: 2024-10-15
- Earliest claimed: 2021-09-27
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Huimei Zhou; Julien Frougier; Xuefeng Liu; Jingyun Zhang; Lan Yu; Heng Wu; Miaomiao Wang; Veeraraghavan S. Basker
- Web page: https://patentgrep.com/patent/US12119341B2

## CPC

- H10D 8/045: {of PN junction diodes}
- H10D 89/611: {using diodes as protective elements}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/128: {Anode regions of diodes}
- H10D 62/129: {Cathode regions of diodes}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8316: {the IGFETs characterised by having gate sidewall spacers specially adapted for integration}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10P 14/3452: {Microstructure}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 12/021: {of gated diodes, e.g. field-controlled diodes [FCD]}
- H10D 12/211: {Gated diodes}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/117: {Shapes of semiconductor bodies}
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

In one embodiment a semiconductor structure comprises a semiconductor substrate, a trench dielectric layer disposed in a trench of the semiconductor substrate, a first source/drain region disposed in contact with the semiconductor substrate, a gate and a second source/drain region. The gate is disposed between the first source/drain region and the second source/drain region. The semiconductor structure further comprises a dielectric isolation layer disposed between the semiconductor substrate and the second source/drain region.

## Claims

### Claim 1

A semiconductor structure, comprising:
a semiconductor substrate;
a trench dielectric layer disposed in a trench of the semiconductor substrate;
an inter-layer dielectric layer disposed on and in contact with the trench dielectric layer;
a first source/drain region of a first conductivity type disposed in contact with the semiconductor substrate;
a gate;
a second source/drain region of a second conductivity type opposite to the first conductivity type, the gate being disposed between the first source/drain region and the second source/drain region;
a first dielectric isolation layer disposed on the semiconductor substrate between a portion having the first conductivity type of the first source/drain region and the trench dielectric layer, and disposed adjacent to and contacting a top surface of a first side of the trench dielectric layer and a bottom surface and a first side surface of the inter-layer dielectric layer; and
a second dielectric isolation layer disposed on the semiconductor substrate between a portion having the second conductivity type of the second source/drain region and the trench dielectric layer, and disposed adjacent to and contacting the top surface of a second side of the trench dielectric layer and the bottom surface and a second side surface opposite to the first side surface of the inter-layer dielectric layer.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the first and second dielectric isolation layers are disposed on the semiconductor substrate adjacent the trench dielectric layer.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, further comprising a first plurality of gates disposed on the semiconductor substrate on the first side of the trench dielectric layer and a second plurality of gates disposed on the semiconductor substrate on the second side of the trench dielectric layer.

### Claim 4 (depends on 3)

The semiconductor structure of claim 3, wherein the first source/drain region corresponds to the first plurality of gates and the second source/drain region corresponds to the second plurality of gates and wherein the first and second source/drain regions and the trench dielectric layer together comprise a diode junction.

### Claim 5

A semiconductor structure, comprising:
a first plurality of gates disposed on a semiconductor substrate on a first side of a trench dielectric layer disposed in a trench of the semiconductor substrate;
an inter-layer dielectric layer disposed on and in contact with the trench dielectric layer;
a first plurality of source/drain regions of a first conductivity type disposed between the first plurality of gates and in contact with the semiconductor substrate;
a second plurality of gates disposed on the semiconductor substrate on a second side of the trench dielectric layer;
a second plurality of source/drain regions of a second conductivity type opposite to the first conductivity type disposed between the second plurality of gates and in contact with the semiconductor substrate;
a first dielectric isolation layer disposed on the semiconductor substrate between a portion having the first conductivity type of the first plurality of source/drain regions and the trench dielectric layer, and disposed adjacent to and contacting a top surface of the first side of the trench dielectric layer and a bottom surface and a first side surface of the inter-layer dielectric layer; and
a second dielectric isolation layer disposed on the semiconductor substrate between a portion having the second conductivity type of the second plurality of source/drain regions and the trench dielectric layer, and disposed adjacent to and contacting the top surface of the second side of the trench dielectric layer and the bottom surface and a second side surface opposite to the first side surface of the inter-layer dielectric layer;
wherein the first plurality of source/drain regions, the second plurality of source/drain regions, the first and second dielectric isolation layers and the trench dielectric layer together form a diode junction.

### Claim 6 (depends on 5)

The semiconductor structure of claim 5, wherein the first and second dielectric isolation layers are disposed on the semiconductor substrate adjacent the trench dielectric layer.

### Claim 7 (depends on 5)

The semiconductor structure of claim 5, further comprising a first source/drain region disposed on the first dielectric isolation layer, the first source/drain region being isolated from the diode junction of the first plurality of source/drain regions, the second plurality of source/drain regions, the first and second dielectric isolation layers and the trench dielectric layer.

### Claim 8 (depends on 7)

The semiconductor structure of claim 7, wherein the first conductivity type comprises one of a p-type and an n-type epitaxy and the second conductivity type comprises the other of the p-type and n-type epitaxy.