# US 12,119,339 B2 · Semiconductor integrated circuit device

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- Number: US 12,119,339 B2
- Document ID: US12119339B2
- Status: Granted
- Kind: B2
- Application number: 18/423,159
- Filed: 2024-01-25
- Published: 2024-05-16
- Granted: 2024-10-15
- Earliest claimed: 2018-11-09
- Assignees: Socionext Inc.
- Applicants: Socionext Inc.
- Inventors: Yoko Shiraki
- Web page: https://patentgrep.com/patent/US12119339B2

## CPC

- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 89/10: Integrated device layouts
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/121: {oriented parallel to substrates}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 88/01: {Manufacture or treatment}
- H10W 20/427: {Power or ground buses}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 84/951: {Technology used, i.e. design rules}
- H10W 20/0698: {Local interconnections}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A layout structure of a standard cell using a complementary FET (CFET) is provided. The standard cell includes a first three-dimensional transistor and a second three-dimensional transistor formed above the first transistor in the depth direction, between buried first and second power supply lines. A first contact connects a local interconnect connected to the first transistor and the first power supply line. A second contact connects a local interconnect connected to the second transistor and the second power supply line. The second contact is longer in the depth direction and greater in size in planar view than the first contact.

## Claims

### Claim 1

A semiconductor integrated circuit device including a standard cell, the standard cell comprising:
a first line extending in a first direction in a first wiring layer;
a second line extending in the first direction in the first wiring layer;
a first transistor that is a three-dimensional transistor of a first conductivity type, formed above the first wiring layer in a depth direction;
a second transistor that is a three-dimensional transistor of a second conductivity type, formed above the first transistor in the depth direction;
a first contact connected to one of a source and a drain of the first transistor and the first line;
a second contact connected to one of a source and a drain of the second transistor and the second line,
wherein
the second contact is longer in the depth direction than the first contact and greater in size in planar view than the first contact.

### Claim 2 (depends on 1)

The semiconductor integrated circuit device of claim 1, wherein
the standard cell comprises:
a gate interconnect extending in a second direction that is a direction perpendicular to the first direction as viewed in plan and also extending in the depth direction, the gate interconnect being to be gates of the first and second transistors.

### Claim 3 (depends on 1)

The semiconductor integrated circuit device of claim 1, wherein
channel portions of the first and second transistors have an overlap as viewed in plan.

### Claim 4 (depends on 1)

The semiconductor integrated circuit device of claim 1, wherein
the standard cell comprises:
a first local interconnect connected to the second contact, the second contact being formed at a position where the second line and the first local interconnect overlap each other as view in plan.

### Claim 5 (depends on 4)

The semiconductor integrated circuit device of claim 4, wherein
the first local interconnect extends in a second direction that is a direction perpendicular to the first direction as viewed in plan and the second contact is longer in the second direction than the first contact.

### Claim 6

A semiconductor integrated circuit device including a standard cell, the standard cell comprising:
a first line extending in a first direction in a first wiring layer;
a first transistor that is a three-dimensional transistor of a first conductivity type, formed above the first wiring layer in a depth direction;
a second transistor that is a three-dimensional transistor of a second conductivity type, formed above the first transistor in the depth direction;
a first local interconnect connected to one of a source and a drain of the first transistor;
a second local interconnect connected to one of a source and a drain of the second transistor;
a first contact formed at a position where the first local interconnect and the second local interconnect overlap each other as viewed in plan, for connecting the first local interconnect and the second local interconnect; and
a second contact connected to another of a source and a drain of the second transistor and the first line,
wherein
the second contact is greater in size in planar view than the first contact.

### Claim 7 (depends on 6)

The semiconductor integrated circuit device of claim 6, wherein
the standard cell comprises:
a gate interconnect extending in a second direction that is a direction perpendicular to the first direction as viewed in plan and also extending in the depth direction, the gate interconnect being to be gates of the first and second transistors.

### Claim 8 (depends on 6)

The semiconductor integrated circuit device of claim 6, wherein
channel portions of the first and second transistors have an overlap as viewed in plan.

### Claim 9 (depends on 6)

The semiconductor integrated circuit device of claim 6, wherein
the first and second local interconnects extend in a second direction that is a direction perpendicular to the first direction as viewed in plan.

### Claim 10 (depends on 9)

The semiconductor integrated circuit device of claim 9, wherein
the second contact is longer in the second direction than the first contact.

### Claim 11 (depends on 6)

The semiconductor integrated circuit device of claim 6, wherein
the standard cell comprises:
a third local interconnect connected to the second contact, the second contact being formed at a position where the first line and the third local interconnect overlap each other as view in plan.