# US 12,119,338 B2 · Semiconductor device packages, packaging methods, and packaged semiconductor devices

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- Number: US 12,119,338 B2
- Document ID: US12119338B2
- Status: Granted
- Kind: B2
- Application number: 18/447,655
- Filed: 2023-08-10
- Published: 2023-12-07
- Granted: 2024-10-15
- Earliest claimed: 2014-07-08
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Jie Chen; Ying-Ju Chen; Hsien-Wei Chen
- Web page: https://patentgrep.com/patent/US12119338B2

## CPC

- H10W 90/00: Package configurations
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 20/031: {of conductive parts of the interconnections}
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/635: {Through-vias}
- H10W 72/90: Bond pads, in general
- H10W 74/01: Manufacture or treatment
- H10W 74/014: {using batch processing}
- H10W 74/016: {using moulds}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto}
- H10W 46/101: {characterised by the type of information, e.g. logos or symbols}
- H10W 46/301: {for alignment}
- H10W 46/607: {Located on parts of packages, e.g. on encapsulations or on package substrates}
- H10W 72/0198: {batch processes}
- H10W 72/075: {of bond wires}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/9413: {on encapsulations}
- H10W 72/951: {Materials of bond pads}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/722: {between stacked chips}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material disposed around the integrated circuit die mounting region. An interconnect structure is disposed over the molding material and the integrated circuit die mounting region. A protection pattern is disposed in a perimeter region of the package. The protection pattern includes a conductive feature.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
forming a protection pattern and conductive redistribution elements located in multiple metallization layers over an encapsulant, the protection pattern being located within a dielectric material isolating the protection pattern;
placing external connections in connection with the conductive redistribution elements, the external connections being the only external connections on a first side of the dielectric material, and wherein the protection pattern is electrically isolated from the external connections; and
bonding a packaged semiconductor device to the external connections.

### Claim 2 (depends on 1)

The method of claim 1, wherein the external connections comprise solder balls.

### Claim 3 (depends on 2)

The method of claim 2, wherein the solder balls are surrounded by a molding compound.

### Claim 4 (depends on 3)

The method of claim 3, wherein the solder balls are surrounded by an underfill.

### Claim 5 (depends on 1)

The method of claim 1, wherein the packaged semiconductor device comprises:
a first semiconductor die;
a second semiconductor die physically bonded to the first semiconductor die; and
a substrate bonded to the second semiconductor die.

### Claim 6 (depends on 5)

The method of claim 5, wherein the first semiconductor die is a memory die.

### Claim 7 (depends on 1)

The method of claim 1, wherein the packaged semiconductor device is a system on chip device.

### Claim 8

A method of manufacturing a semiconductor device, the method comprising:
forming a conductive redistribution layer extending over both a first semiconductor device and an encapsulant adjacent to the first semiconductor device;
forming a protection pattern located over the encapsulant, the protection pattern comprising a second conductive material that is electrically isolated from all elements below a surface of the encapsulant, the surface of the encapsulant facing the protection pattern, the protection pattern comprising a first conductive feature and a second conductive feature, the second conductive feature being separated from the first conductive feature by a dielectric material in a direction extending away from the encapsulant, wherein the dielectric material electrically isolates the protection pattern; and
electrically connecting a package-on-package device to the first semiconductor device.

### Claim 9 (depends on 8)

The method of claim 8, wherein the package-on-package device is a system-on-chip device.

### Claim 10 (depends on 8)

The method of claim 8, wherein the package-on-package device comprises:
a substrate;
a first semiconductor device bonded to the substrate; and
a second semiconductor device bonded to the first semiconductor device and electrically connected to the substrate.

### Claim 11 (depends on 10)

The method of claim 10, wherein the second semiconductor device is electrically connected to the substrate through a first wire bond.

### Claim 12 (depends on 11)

The method of claim 11, wherein the first semiconductor device is electrically connected to the substrate through a second wire bond different from the first wire bond.

### Claim 13 (depends on 12)

The method of claim 12, further comprising encapsulating the first wire bond and the second wire bond.

### Claim 14 (depends on 8)

The method of claim 8, wherein the package-on-package device comprises a memory device.

### Claim 15

A method of manufacturing a semiconductor device, the method comprising:
bonding a substrate to external connectors in electrical connection with a plurality of first conductive layers over both a semiconductor die and an encapsulant, wherein individual layers of the plurality of first conductive layers are aligned in a horizontal direction as seen in a cross-sectional view with respective ones of a plurality of second conductive layers overlying the encapsulant, wherein a dielectric material completely electrically isolates the plurality of second conductive layers from the plurality of first conductive layers and from the encapsulant, wherein each pad located on a side of the substrate facing the semiconductor die is connected to a respective one of the external connectors, wherein the substrate connects a first memory chip and a second memory chip to the external connectors; and
connecting a printed circuit board to the semiconductor die, the printed circuit board being located on an opposite side of the semiconductor die from the substrate.

### Claim 16 (depends on 15)

The method of claim 15, wherein the external connectors comprise solder.

### Claim 17 (depends on 15)

The method of claim 15, wherein the first memory chip is connected to the substrate with a first wire bond.

### Claim 18 (depends on 17)

The method of claim 17, wherein the second memory chip is connected to the substrate with a second wire bond.

### Claim 19 (depends on 15)

The method of claim 15, wherein the connecting the printed circuit board to the semiconductor die is performed at least in part with solder balls.

### Claim 20 (depends on 15)

The method of claim 15, further comprising applying an underfill around the external connectors.