# US 12,119,337 B2 · Method of manufacturing a semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,119,337 B2 - Document ID: US12119337B2 - Status: Granted - Kind: B2 - Application number: 18/298,104 - Filed: 2023-04-10 - Published: 2023-09-07 - Granted: 2024-10-15 - Earliest claimed: 2020-03-23 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Junichi Shibata - Web page: https://patentgrep.com/patent/US12119337B2 ## CPC - H10W 90/00: Package configurations - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00) - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10W 72/0198: {batch processes} - H10W 80/00: Direct bonding of chips, wafers or substrates - H10W 72/07327: {involving guiding structures, e.g. spacers or supporting members} - H10W 72/07332: {Compression bonding, e.g. thermocompression bonding} - H10W 72/07353: {changes in shapes} - H10W 72/332: {Plan-view shape, i.e. in top view} - H10W 72/334: {Cross-sectional shape, i.e. in side view} - H10W 72/941: {Dispositions of bond pads} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 80/102: {Controlling the environment during the bonding, e.g. the temperature or pressure} - H10W 80/163: {using active alignment, e.g. detecting marks and correcting position} - H10W 80/312: {characterised by the direct bonding of electrically conductive pads} - H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers} - H10W 80/334: {Thermocompression bonding} - H10W 80/732: {having shape changed during the connecting} - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/732: {between stacked chips} - H10W 90/792: {between multiple chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A semiconductor device has a first substrate including an element region, a peripheral region that surrounds the element region, a first insulator with a first recess portion in the peripheral region, a first metal layer in the element region, and a first conductor in the peripheral region to surround the element region. A second substrate has an element region, a peripheral region that surrounds the element region, a second insulator with a second recess portion that faces the first recess portion, a second metal layer in contact with the first metal layer, and a second conductor that surrounds the element region of the second substrate. ## Claims ### Claim 1 A manufacturing method of a semiconductor device, comprising: attaching a first substrate to a second substrate, wherein the first substrate includes: a first element region, a first peripheral region that surrounds the first element region, a first insulator in the first element region and the first peripheral region and having a first recess portion in the first peripheral region, a first metal layer in the first element region and exposed at an uppermost surface of the first substrate, a first conductor in the first peripheral region in the first insulator below the uppermost surface of the first substrate, the first conductor surrounding the first element region, and a first insulating layer between the first conductor and the interface between the first substrate and the second substrate, the first insulating layer comprising silicon and nitrogen; the second substrate includes: a second element region, a second peripheral region that surrounds the second element region, a second insulator in the second element region and the second peripheral region, the second insulator having a second recess portion in the second peripheral region, a second metal layer in the second element region and exposed at an uppermost surface of the second substrate, a second conductor in the second peripheral region in the second insulator below the uppermost surface of the second substrate, the second conductor surrounding the second element region, and a second insulating layer between the second conductor and the interface between the first substrate and the second substrate, the second insulating layer comprising silicon and nitrogen; and after the first substrate and the second substrate are attached, the first metal layer and the second metal layer directly contact one another, and the first recess portion and the second recess portion are connected to one another. ### Claim 2 (depends on 1) The manufacturing method of the semiconductor device according to claim 1, wherein the first recess portion and the second recess portion form a cavity after the first and second substrates are attached. ### Claim 3 (depends on 2) The manufacturing method of the semiconductor device according to claim 2, wherein the cavity surrounds both the first metal layer and the second metal layer. ### Claim 4 (depends on 1) The manufacturing method of the semiconductor device according to claim 1, wherein the first recess portion completely encircles the first element region, and the second recess portion completely encircles the second element region. ### Claim 5 (depends on 1) The manufacturing method of the semiconductor device according claim 1, wherein the first substrate further includes a first semiconductor layer, the first insulator being between the first semiconductor layer and the second substrate, and the first conductor contacts the first semiconductor layer. ### Claim 6 (depends on 1) The manufacturing method of the semiconductor device according to claim 1, wherein a distance between a bottom surface of the first recess portion and the uppermost surface of the first substrate is greater than a distance between the first conductor and the uppermost surface of the first substrate. ### Claim 7 (depends on 1) The manufacturing method of the semiconductor device according to claim 1, wherein the first conductor is exposed at the bottom surface of the first recess portion. ### Claim 8 (depends on 1) The manufacturing method of the semiconductor device according to claim 1, wherein a distance between a bottom surface of the first recess portion and the uppermost surface of the first substrate is less than a distance between the first insulating layer and the uppermost surface of the first substrate. ### Claim 9 (depends on 1) The manufacturing method of the semiconductor device according to claim 1, wherein the first substrate further includes a third conductor in the first insulator in the first peripheral region, the third conductor is closer to the first element region than is the first conductor, the first recess portion is between the first conductor and the third conductor, the second substrate further includes a fourth conductor in the second insulator in the second peripheral region, the fourth conductor is closer to the second element region than is the second conductor, and the second recess portion is between the second conductor and the fourth conductor. ### Claim 10 (depends on 1) The manufacturing method of the semiconductor device according to claim 1, wherein the first element region includes a control circuit, and the second element region includes a memory cell array that is controlled by the control circuit. ### Claim 11 (depends on 10) The manufacturing method of the semiconductor device according to claim 10, wherein the first metal layer is electrically connected to the control circuit, and the second metal layer is electrically connected to the memory cell array. ### Claim 12 (depends on 1) The manufacturing method of the semiconductor device according to claim 1, wherein a thickness of at least one of the first substrate and the second substrate in a direction perpendicular to the interface between the first substrate and the second substrate is at least 5 μm. ### Claim 13 (depends on 1) The manufacturing method of the semiconductor device according to claim 1, wherein the first insulating layer is on the first conductor, and the second insulating layer is on the second conductor. ### Claim 14 (depends on 1) The manufacturing method of the semiconductor device according to claim 1, wherein the first substrate further includes a third insulating layer between the first insulating layer and the interface between the first substrate and the second substrate, and the second substrate further includes a fourth insulating layer between the second insulating layer and the interface between the first substrate and the second substrate. ### Claim 15 (depends on 1) The manufacturing method of the semiconductor device according to claim 1, wherein the first insulating layer and the second insulating layer comprise silicon nitride. ### Claim 16 (depends on 1) The manufacturing method of the semiconductor device according to claim 1, wherein the first insulating layer and the second insulating comprise nitrogen doped silicon carbide. ### Claim 17 A manufacturing method of a semiconductor device, comprising: bonding a first wafer and a second wafer; and cutting the first wafer and the second wafer into dies after bonding, wherein the first wafer includes: a first element region, a first peripheral region that surrounds the first element region, a first insulator in the first element region and the first peripheral region and having a first recess portion in the first peripheral region, a first metal layer in the first element region and exposed at an uppermost surface of the first wafer, a first conductor in the first peripheral region in the first insulator below the uppermost surface of the first wafer, the first conductor surrounding the first element region, and a first insulating layer between the first conductor and the interface between the first wafer and the second wafer, the first insulating layer comprising silicon and nitrogen; the second wafer includes: a second element region, a second peripheral region that surrounds the second element region, a second insulator in the second element region and the second peripheral region, the second insulator having a second recess portion in the second peripheral region, a second metal layer in the second element region and exposed at an uppermost surface of the second wafer, a second conductor in the second peripheral region in the second insulator below the uppermost surface of the second wafer, the second conductor surrounding the second element region, and a second insulating layer between the second conductor and the interface between the first wafer and the second wafer, the second insulating layer comprising silicon and nitrogen; and after the first wafer and the second wafer are bonded, the first metal layer and the second metal layer directly contact one another, and the first recess portion and the second recess portion are connected to one another. ### Claim 18 (depends on 17) The manufacturing method of the semiconductor device according to claim 17, wherein the first insulating layer is on the first conductor, and the second insulating layer is on the second conductor. ### Claim 19 (depends on 17) The manufacturing method of the semiconductor device according to claim 17, wherein the first wafer further includes a third insulating layer between the first insulating layer and the interface between the first wafer and the second wafer, and the second wafer further includes a fourth insulating layer between the second insulating layer and the interface between the first wafer and the second wafer. ### Claim 20 (depends on 17) The manufacturing method of the semiconductor device according to claim 17, wherein the first insulating layer and the second insulating layer comprise nitrogen doped silicon carbide.