# US 12,119,336 B2 · Fusion memory device and method of fabricating the same

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- Number: US 12,119,336 B2
- Document ID: US12119336B2
- Status: Granted
- Kind: B2
- Application number: 17/883,682
- Filed: 2022-08-09
- Published: 2022-12-01
- Granted: 2024-10-15
- Earliest claimed: 2018-12-21
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Hyunmog Park; Daehyun Kim; Jinmin Kim; Hei Seung Kim; Hyunsik Park; Sangkil Lee
- Web page: https://patentgrep.com/patent/US12119336B2

## CPC

- G11C 11/005: {comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells}
- H10W 90/00: Package configurations
- G11C 14/0018: {whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor}
- G11C 16/04: using variable threshold transistors, e.g. FAMOS
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/40: characterised by the peripheral circuit region
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/42: Vias, e.g. via plugs
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10B 63/845: {the switching components being connected to a common vertical conductor}
- H10W 72/29: Bond pads specially adapted therefor
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Disclosed are fusion memory devices and methods of fabricating the same. The fusion memory device comprises a first memory device including a first substrate having active and inactive surfaces opposite to each other and a first memory cell circuit on the active surface of the first substrate, a non-memory device including a second substrate having active and inactive surfaces opposite to each other and a non-memory circuit on the active surface of the second substrate, the non-memory device being provided on the first memory device, and a second memory device on the inactive surface of the second substrate and including a second memory cell circuit different from the first memory cell circuit. The non-memory device lies between the first and second memory cell circuits and controls an electrical operation of each of the first and second memory cell circuits.

## Claims

### Claim 1

A method of fabricating a fusion memory device, the method comprising:
forming a first memory cell circuit including a plurality of first memory cells on an active surface of a first substrate;
forming a non-memory circuit including a plurality of conductive lines on an active surface of a second substrate;
combining the first memory cell circuit with the non-memory circuit; and
forming a second memory cell circuit including a plurality of second memory cells on an inactive surface of the second substrate,
wherein forming the first memory cell circuit and forming the non-memory circuit are performed independently of each other, and
wherein forming the first memory cell circuit is performed at a first temperature higher than a second temperature of forming the second memory cell circuit, and
wherein forming the second memory cell circuit does not include a diffusion process.

### Claim 2 (depends on 1)

The method of claim 1, wherein combining the first memory cell circuit with the non-memory circuit includes combining the first substrate and the second substrate with each other to allow the active surface of the second substrate to face the active surface of the first substrate.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
after combining the first memory cell circuit with the non-memory circuit, thinning the second substrate physically or chemically.

### Claim 4 (depends on 1)

The method of claim 1, wherein forming the first memory cell circuit includes:
vertically stacking a plurality of gate electrodes on the active surface of the first substrate;
forming a plurality of vertical channels vertically penetrating the plurality of gate electrodes, each of the vertical channels being surrounded by a memory layer; and
forming a plurality of electrical lines electrically connected to the vertical channels.

### Claim 5 (depends on 4)

The method of claim 4, wherein forming the first memory cell circuit further includes:
performing a diffusion process on the active surface of the first substrate at the first temperature; and
forming a plurality of common source plugs electrically connected to the active surface of the first substrate.

### Claim 6 (depends on 5)

The method of claim 5, wherein the first temperature is higher than 800° C.

### Claim 7 (depends on 1)

The method of claim 1, wherein forming the second memory cell circuit includes:
forming a plurality of word lines horizontally arranged on the inactive surface of the second substrate;
forming a plurality of bit lines on the word lines, the bit lines intersecting the word lines; and
forming a plurality of variable resistance layers on corresponding intersections between the word lines and the bit lines.

### Claim 8 (depends on 7)

The method of claim 7,
wherein forming the second memory cell circuit further includes forming a plurality of through electrodes electrically connecting the word and bit lines to the conductive lines of the non-memory circuit, and
wherein the plurality of through electrodes vertically penetrates the second substrate.

### Claim 9

A method of fabricating a fusion memory device, the method comprising:
forming a first memory cell circuit including a plurality of first memory cells on an active surface of a first substrate;
forming a non-memory circuit including a plurality of peripheral transistors on an active surface of a second substrate, and a plurality of conductive lines electrically connected to the peripheral transistors; and
combining the first memory cell circuit with the non-memory circuit,
wherein forming the first memory cell circuit includes:
performing a diffusion process on the active surface of the first substrate at a first temperature;
vertically stacking a plurality of gate electrodes on the active surface of the first substrate;
forming a plurality of vertical channels vertically penetrating the plurality of gate electrodes, each of the vertical channels being surrounded by a memory layer;
forming a plurality of common source plugs electrically connected to the active surface of the first substrate; and
forming a plurality of electrical lines electrically connected to the gate electrodes, the vertical channels, and the common source plugs,
wherein combining the first memory cell circuit with the non-memory circuit includes:
aligning a first outer terminal of the first memory cell circuit, which is electrically connected to at least one of the electrical lines, with a second outer terminal of the non-memory circuit, which is electrically connected to at least one of the conductive lines; and
bonding the first outer terminal to the second outer terminal.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
forming a second memory cell circuit including a plurality of second memory cells on an inactive surface of the second substrate,
wherein forming the second memory cell circuit is performed at a second temperature lower than the first temperature.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
after combining the first memory cell circuit with the non-memory circuit, thinning the second substrate physically or chemically.

### Claim 12 (depends on 10)

The method of claim 10,
wherein forming the second memory cell circuit includes forming a plurality of through electrodes electrically connected to the conductive lines of the non-memory circuit, and
wherein the plurality of through electrodes vertically penetrates the second substrate.

### Claim 13 (depends on 10)

The method of claim 10, wherein forming the second memory cell circuit includes:
forming a plurality of word lines horizontally arranged on the inactive surface of the second substrate;
forming a plurality of bit lines on the word lines, the bit lines intersecting the word lines; and
forming a plurality of variable resistance layers on corresponding intersections between the word lines and the bit lines.

### Claim 14 (depends on 9)

The method of claim 9, wherein the first memory cell circuit is physically and electrically connected to the non-memory circuit through the first and second outer terminals that are bonded to each other.

### Claim 15

A method of fabricating a fusion memory device, the method comprising:
forming a first memory cell circuit including a plurality of first memory cells on an active surface of a first semiconductor substrate;
forming a non-memory circuit including a plurality of conductive lines on an active surface of a second semiconductor substrate;
combining the first memory cell circuit with the non-memory circuit; and
forming a second memory cell circuit including a plurality of second memory cells on an inactive surface of the second semiconductor substrate,
wherein forming the first memory cell circuit includes:
performing a diffusion process on the active surface of the first semiconductor substrate at a first temperature; and
forming a plurality of common source plugs electrically connected to the active surface of the first semiconductor substrate, and
wherein forming the second memory cell circuit excludes a diffusion process.

### Claim 16 (depends on 15)

The method of claim 15, wherein forming the second memory cell circuit is performed at a second temperature lower than the first temperature.

### Claim 17 (depends on 15)

The method of claim 15, wherein combining the first memory cell circuit with the non-memory circuit includes combining the first semiconductor substrate and the second semiconductor substrate with each other to allow the active surface of the second semiconductor substrate to face the active surface of the first semiconductor substrate.

### Claim 18 (depends on 15)

The method of claim 15, further comprising:
after combining the first memory cell circuit with the non-memory circuit, thinning the second semiconductor substrate physically or chemically.

### Claim 19 (depends on 15)

The method of claim 15, wherein forming the first memory cell circuit further includes:
vertically stacking a plurality of gate electrodes on the active surface of the first semiconductor substrate;
forming a plurality of vertical channels vertically penetrating the plurality of gate electrodes, each of the vertical channels being surrounded by a memory layer; and
forming a plurality of electrical lines electrically connected to the gate electrodes, the vertical channels, and the common source plugs.

### Claim 20 (depends on 15)

The method of claim 15, wherein forming the second memory cell circuit includes:
forming a plurality of word lines horizontally arranged on the inactive surface of the second semiconductor substrate;
forming a plurality of bit lines on the word lines, the bit lines intersecting the word lines; and
forming a plurality of variable resistance layers on corresponding intersections between the word lines and the bit lines.