# US 12,119,335 B2 · Interconnection structures for high bandwidth data transfer

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- Number: US 12,119,335 B2
- Document ID: US12119335B2
- Status: Granted
- Kind: B2
- Application number: 17/552,754
- Filed: 2021-12-16
- Published: 2023-06-22
- Granted: 2024-10-15
- Earliest claimed: 2021-12-16
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Joshua M Rubin; Steven Lorenz Wright; Arvind Kumar; Mounir Meghelli
- Web page: https://patentgrep.com/patent/US12119335B2

## CPC

- H10W 90/00: Package configurations
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/685: comprising multiple insulating layers
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments of one or more high bandwidth chips (HB chips), e.g., high bandwidth memories (HBMs), are mounted on a module substrate. The HB chips/HBMs each have one or more HBM parallel communication interfaces (HB chip PHYs or HBM PHYs, respectively) that are connected to a companion PHY through a compatible companion PHY parallel connection that enable communication between the HBM PHY and the companion PHY. A companion PHY parallel link connection connects to a SERDES parallel connection of a SERDES. The SERDES converts parallel data/information at the SERDES parallel connection to serial data/information at a SERDES serial connection, and visa-versa, that enables efficient high bandwidth data transfer over longer distances. Alternative embodiments are disclosed.

## Claims

### Claim 1

A semiconductor memory module comprising:
a module substrate comprising active components and passive components, wherein the active components comprise companion physical layers, a memory controller, a SERDES, and an I/O connection,
wherein the SERDES and the I/O connection are communicatively coupled with a serial communication link, and
wherein the I/O connection is located a communication distance greater than 8 mm from the companion physical layers;
a high bandwidth semiconductor chip comprising a physical layer physically secured to the module substrate, wherein the physical layer of the high bandwidth semiconductor chip is communicatively coupled to the SERDES via a companion parallel connection, the companion physical layers, a parallel communication link, and the memory controller.

### Claim 2 (depends on 1)

The semiconductor memory module according to claim 1, wherein the module substrate is an active bridge.

### Claim 3 (depends on 1)

The semiconductor memory module according to claim 1, wherein the module substrate is a passive bridge.

### Claim 4 (depends on 1)

The semiconductor memory module according to claim 1, wherein the SERDES is communicatively coupled to the I/O connection via the serial communication link.

### Claim 5 (depends on 1)

The semiconductor memory module according to claim 1, wherein the companion parallel connection provides an interface between the physical layer of the high bandwidth semiconductor chip and the companion physical layers of the module substrate.

### Claim 6 (depends on 1)

The semiconductor memory module according to claim 1, wherein the companion physical layers, the parallel communication link, the memory controller, and the SERDES are located within the module substrate.

### Claim 7 (depends on 1)

The semiconductor memory module according to claim 1, wherein the physical layer is located within the high bandwidth semiconductor chip.

### Claim 8

A semiconductor memory module comprising:
a module substrate comprising active components and passive components, wherein the active components comprise companion physical layers, a SERDES, and an I/O connection,
wherein the SERDES and the I/O connection are communicatively coupled with a serial communication link, and
wherein the I/O connection is located a communication distance greater than 8 mm from the companion physical layers;
a high bandwidth semiconductor chip comprising a physical layer physically secured to the module substrate, wherein the physical layer of the high bandwidth semiconductor chip is communicatively coupled to the SERDES via a companion parallel connection, the companion physical layers, and a parallel communication link.

### Claim 9 (depends on 8)

The semiconductor memory module according to claim 8, wherein the module substrate is an active bridge.

### Claim 10 (depends on 8)

The semiconductor memory module according to claim 8, wherein the module substrate is a passive bridge.

### Claim 11 (depends on 8)

The semiconductor memory module according to claim 8, wherein the SERDES is communicatively coupled to the I/O connection via the serial communication link.

### Claim 12 (depends on 8)

The semiconductor memory module according to claim 8, wherein the companion parallel connection provides an interface between the physical layer of the high bandwidth semiconductor chip and the companion physical layers of the module substrate.

### Claim 13 (depends on 8)

The semiconductor memory module according to claim 8, wherein the companion physical layers, the parallel communication link, and the SERDES are located within the module substrate.

### Claim 14 (depends on 8)

The semiconductor memory module according to claim 8, wherein the physical layer is located within the high bandwidth semiconductor chip.

### Claim 15

A semiconductor memory module comprising:
a module substrate comprising active components and passive components, wherein the active components comprise companion physical layers, a SERDES, and an I/O connection, wherein the SERDES and the I/O connection are communicatively coupled with a serial communication link, and
a high bandwidth semiconductor chip comprising a physical layer physically secured to the module substrate, wherein the physical layer of the high bandwidth semiconductor chip is communicatively coupled to the SERDES via a companion parallel connection, the companion physical layers, and a parallel communication link.

### Claim 16 (depends on 15)

The semiconductor memory module according to claim 15, wherein the module substrate is an active bridge.

### Claim 17 (depends on 15)

The semiconductor memory module according to claim 15, wherein the module substrate is a passive bridge.

### Claim 18 (depends on 15)

The semiconductor memory module according to claim 15, wherein the SERDES is communicatively coupled to the I/O connection via the serial communication link.

### Claim 19 (depends on 15)

The semiconductor memory module according to claim 15, wherein the companion parallel connection provides an interface between the physical layer of the high bandwidth semiconductor chip and the companion physical layers of the module substrate.

### Claim 20 (depends on 15)

The semiconductor memory module according to claim 15, wherein the companion physical layers, the parallel communication link, and the SERDES are located within the module substrate.

### Claim 21 (depends on 15)

The semiconductor memory module according to claim 15, wherein the physical layer is located within the high bandwidth semiconductor chip.