# US 12,119,331 B2 · Semiconductor package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,119,331 B2 - Document ID: US12119331B2 - Status: Granted - Kind: B2 - Application number: 17/677,453 - Filed: 2022-02-22 - Published: 2022-12-15 - Granted: 2024-10-15 - Earliest claimed: 2021-06-14 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Ju-Il Choi; Gyuho Kang; Heewon Kim; Sechul Park; Jongho Park; Junyoung Park - Web page: https://patentgrep.com/patent/US12119331B2 ## CPC - H10W 90/00: Package configurations - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 70/611: {for connecting multiple chips together} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/685: comprising multiple insulating layers - H10W 80/00: Direct bonding of chips, wafers or substrates - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/635: {Through-vias} - H10W 80/312: {characterised by the direct bonding of electrically conductive pads} - H10W 90/288: {characterised by arrangements for thermal management of the stacked chips} - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Disclosed is a semiconductor package comprising an interposer substrate having first and second surfaces opposite each other and including a wiring layer adjacent to the first surface, a semiconductor chip on the first surface of the interposer substrate, a passivation layer on the first surface of the interposer substrate and covering the semiconductor chip, and redistribution patterns in the passivation layer and connected to the semiconductor chip. The semiconductor chip has third and fourth surfaces opposite to each other. The third surface of the semiconductor chip faces the first surface of the interposer substrate. The redistribution patterns are connected to the fourth surface of the semiconductor chip. The semiconductor chip includes chip pads adjacent to the third surface and chip through electrodes connected to the chip pads. Each of the chip pads is directly bonded to a corresponding one of wiring patterns in the wiring layer. ## Claims ### Claim 1 A semiconductor package, comprising: an interposer substrate having a first surface and a second surface that are opposite to each other, the interposer substrate including a wiring layer adjacent to the first surface and a plurality of through electrodes that penetrate the interposer substrate and connect to the wiring layer, each of the plurality of through electrodes extending from the wiring layer toward the second surface; a semiconductor chip on the first surface of the interposer substrate; a passivation layer on the first surface of the interposer substrate, the passivation layer covering the semiconductor chip; and a plurality of redistribution patterns in the passivation layer and connected to the semiconductor chip, wherein the semiconductor chip has a third surface and a fourth surface that are opposite to each other, the third surface of the semiconductor chip faces the first surface of the interposer substrate, and the plurality of redistribution patterns are connected to the fourth surface of the semiconductor chip, wherein the semiconductor chip includes: a plurality of chip pads adjacent to the third surface; a semiconductor substrate on the plurality of chip pads; a plurality of chip through electrodes penetrating the semiconductor substrate and spaced apart from each other in the semiconductor substrate; a circuit layer on the semiconductor substrate; and a chip wiring layer on the circuit layer and adjacent to the fourth surface, wherein the plurality of chip through electrodes are connected to the plurality of chip pads, wherein each of the plurality of chip pads is directly connected to a corresponding one of a plurality of wiring patterns in the wiring layer of the interposer substrate, and wherein the plurality of redistribution patterns are connected to a plurality of chip wiring patterns in the chip wiring layer. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the circuit layer is between the chip wiring layer and the plurality of chip through electrodes, and wherein the plurality of chip through electrodes and the plurality of chip wiring patterns in the chip wiring layer are connected to the circuit layer. ### Claim 3 (depends on 2) The semiconductor package of claim 2, wherein the plurality of chip through electrodes are between the circuit layer and the plurality of chip pads. ### Claim 4 (depends on 1) The semiconductor package of claim 1, wherein each of the plurality of redistribution patterns and the plurality of chip wiring patterns in the chip wiring layer has a thickness in a direction perpendicular to the first surface of the interposer substrate, and wherein the thickness of each of the plurality of redistribution patterns is greater than the thickness of each of the plurality of chip wiring patterns. ### Claim 5 (depends on 1) The semiconductor package of claim 1, wherein each of the plurality of redistribution patterns and the plurality of wiring patterns in the wiring layer of the interposer substrate has a thickness in a direction perpendicular to the first surface of the interposer substrate, and wherein the thickness of each of the plurality of redistribution patterns is greater than the thickness of each of the plurality of wiring patterns. ### Claim 6 (depends on 1) The semiconductor package of claim 1, wherein a size of each of the plurality of through electrodes included in the interposer substrate is greater than a size of each of the plurality of chip through electrodes included in the semiconductor chip. ### Claim 7 (depends on 1) The semiconductor package of claim 1, wherein the wiring layer of the interposer substrate includes a wiring dielectric layer that covers the plurality of wiring patterns, and the semiconductor chip further includes a pad dielectric layer that covers the plurality of chip pads, and wherein the pad dielectric layer is in direct contact with wiring dielectric layer in the wiring layer. ### Claim 8 A semiconductor package, comprising: an interposer substrate having a first surface and a second surface that are opposite to each other, the interposer substrate including a wiring layer adjacent to the first surface; a first semiconductor chip and a second semiconductor chip that are horizontally spaced apart from each other on the first surface of the interposer substrate; a passivation layer on the first surface of the interposer substrate, the passivation layer covering the first semiconductor chip and the second semiconductor chip; and a plurality of redistribution patterns in the passivation layer, the plurality of redistribution patterns connecting the first semiconductor chip to the second semiconductor chip, wherein the first semiconductor chip has a third surface and a fourth surface that are opposite to each other, the first semiconductor chip including: a plurality of first chip pads adjacent to the third surface; a first semiconductor substrate on the plurality of first chip pads; a plurality of first chip through electrodes penetrating the first semiconductor substrate and spaced apart from each other in the first semiconductor substrate; and a first circuit layer on the first semiconductor substrate, wherein the second semiconductor chip has a fifth surface and a sixth surface that are opposite to each other, the second semiconductor chip including: a plurality of second chip pads adjacent to the fifth surfaces; a second semiconductor substrate on the plurality of second chip pads; a plurality of second chip through electrodes penetrating the second semiconductor substrate and spaced apart from each other in the second semiconductor substrate; and a second circuit layer on the second semiconductor substrate, wherein each of the plurality of first chip pads and the plurality of second chip pads are directly connected to a corresponding one of a plurality of wiring patterns in the wiring layer of the interposer substrate, and wherein the plurality of redistribution patterns are connected to the fourth surface of the first semiconductor chip and to the sixth surface of the second semiconductor chip. ### Claim 9 (depends on 8) The semiconductor package of claim 8, wherein the interposer substrate further includes a plurality of through electrodes that penetrate the interposer substrate, and wherein each of the plurality of through electrodes connects to the wiring layer and extends from the wiring layer toward the second surface. ### Claim 10 (depends on 9) The semiconductor package of claim 9, wherein the first semiconductor chip further includes a first chip wiring layer adjacent to the fourth surface, the first circuit layer between the first chip wiring layer and the first semiconductor substrate, and the second semiconductor chip further includes a second chip wiring layer adjacent to the sixth surface, the second circuit layer between the second chip wiring layer and the second semiconductor substrate. ### Claim 11 (depends on 10) The semiconductor package of claim 10, wherein the plurality of redistribution patterns are connected to a plurality of first chip wiring patterns in the first chip wiring layer of the first semiconductor chip and to a plurality of second chip wiring patterns in the second chip wiring layer of the second semiconductor chip. ### Claim 12 (depends on 8) The semiconductor package of claim 8, wherein the plurality of first chip through electrodes are connected to the first circuit layer and the plurality of first chip pads, and the plurality of second chip through electrodes are connected to the second circuit layer and the plurality of second chip pads. ### Claim 13 (depends on 9) The semiconductor package of claim 9, wherein a size of each of the plurality of through electrodes included in the interposer substrate is greater than a size of each of the plurality of first and the plurality of second chip through electrodes. ### Claim 14 (depends on 8) The semiconductor package of claim 8, wherein each of the plurality of redistribution patterns and the plurality of wiring patterns in the wiring layer of the interposer substrate has a thickness in a direction perpendicular to the first surface of the interposer substrate, and wherein the thickness of each of the plurality of redistribution patterns is greater than the thickness of each of the plurality of wiring patterns. ### Claim 15 (depends on 8) The semiconductor package of claim 8, wherein the first semiconductor chip and the second semiconductor chip are the same as each other. ### Claim 16 A semiconductor package, comprising: an interposer substrate having a first surface and a second surface that are opposite to each other, the interposer substrate including a wiring layer adjacent to the first surface; a first semiconductor chip and a second semiconductor chip that are horizontally spaced apart from each other on the first surface of the interposer substrate; a passivation layer on the first surface of the interposer substrate, the passivation layer covering the first semiconductor chip and the second semiconductor chip; a third semiconductor chip on the passivation layer; a plurality of conductive pillars below the third semiconductor chip; and a plurality of redistribution patterns in the passivation layer, the plurality of redistribution patterns connecting the first semiconductor chip to the second semiconductor chip, wherein the first semiconductor chip has a third surface and a fourth surface that are opposite to each other, the first semiconductor chip including a plurality of first chip pads adjacent to the third surface, wherein the second semiconductor chip has a fifth surface and a sixth surface that are opposite to each other, the second semiconductor chip including a plurality of second chip pads adjacent to the fifth surface, wherein each of the plurality of first chip pads and the plurality of second chip pads are directly bonded to a corresponding one of a plurality of wiring patterns in the wiring layer, wherein the plurality of redistribution patterns are connected to the fourth surface of the first semiconductor chip and to the sixth surface of the second semiconductor chip, wherein the plurality of conductive pillars penetrate through the passivation layer and connect with the wiring layer of the interposer substrate, and wherein the plurality of conductive pillars are connected to corresponding ones of the plurality of wiring patterns in the wiring layer. ### Claim 17 (depends on 16) The semiconductor package of claim 16, wherein the first semiconductor chip and the second semiconductor chip are the same as each other, and the third semiconductor chip is different from the first semiconductor chip and the second semiconductor chip. ### Claim 18 (depends on 16) The semiconductor package of claim 16, wherein each of the first semiconductor chip, the second semiconductor chip, and the plurality of conductive pillars has a thickness in a direction perpendicular to the first surface of the interposer substrate, and wherein the thickness of each of the plurality of conductive pillars is greater than the thickness of each of the first semiconductor chip and the second semiconductor chip.