# US 12,119,329 B2 · Semiconductor package and method of fabricating the same

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- Number: US 12,119,329 B2
- Document ID: US12119329B2
- Status: Granted
- Kind: B2
- Application number: 18/448,284
- Filed: 2023-08-11
- Published: 2023-11-30
- Granted: 2024-10-15
- Earliest claimed: 2019-10-30
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Eunkyul Oh; Yunrae Cho; Taeheon Kim; Seunghun Han
- Web page: https://patentgrep.com/patent/US12119329B2

## CPC

- H10W 90/00: Package configurations
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects}
- H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 74/016: {using moulds}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/263: {Providing mechanical bonding or support, e.g. dummy bumps}
- H10W 72/267: {Multiple bump connectors having different functions}
- H10W 72/387: {Flow barriers}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/284: {characterised by structural arrangements for measuring or testing}
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure relates to a semiconductor package and a manufacturing method thereof. The method includes stacking semiconductor chips using a thermo-compression bonding (TCB) method, where defects are minimized for increased reliability. The semiconductor package includes an interface chip including a first test pad, a bump pad provided inside the first test pad, and a first through silicon via (TSV) provided between the first test pad and the bump pad; at least one memory chip, which is stacked on the interface chip and includes a second test pad, a dummy pad provided inside the second test pad, and a second TSV provided between the second test pad and the dummy pad; and an adhesive layer provided between the interface chip and the at least one memory chip. wherein no bump is provided on the first test pad and the second test pad.

## Claims

### Claim 1

A semiconductor package comprising:
an interface chip comprising a first pad provided in an outer portion of the interface chip, a second pad provided inside the first pad, and a first through silicon via (TSV) provided between the first pad and the second pad;
at least one memory chip stacked on the interface chip, wherein the at least one memory chip comprises a third pad provided in an outer portion of the at least one memory chip, a fourth pad provided inside the third pad, and a second TSV provided between the third pad and the fourth pad; and
an adhesive layer provided between the interface chip and the at least one memory chip,
wherein a first bump is provided on the second pad on a bottom surface of the interface chip,
a second bump is provided on the second TSV on a bottom surface of the at least one memory chip,
a dummy bump is provided on the bottom surface of the at least one memory chip to be adjacent to the second bump, and
each of the first pad and the third pad comprises a groove.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein,
when a minimum pitch between adjacent second TSVs or adjacent second bumps is denoted as A and a distance between the second bump and the dummy bump is denoted as B, the dummy bump is configured to satisfy A≤B≤2A.

### Claim 3 (depends on 2)

The semiconductor package of claim 2,
wherein, when a distance between the third pad and the second bump is greater than 2A, the dummy bump is provided on the at least one memory chip between the third pad and the second bump, and, when a distance between the third pad and the dummy bump adjacent thereto is denoted as C, the dummy bump is configured to satisfy A≤C.

### Claim 4 (depends on 3)

The semiconductor package of claim 3, wherein the adhesive layer includes a non-conductive film (NCF) and has a structure protruding outward from side surfaces of the interface chip and the at least one memory chip.

### Claim 5 (depends on 2)

The semiconductor package of claim 2, wherein a first dummy bump, the second bump, a second dummy bump, and the third pad are arranged in an order stated in a first direction from a center of the at least one memory chip toward an outside,
first dummy bumps, second bumps, second dummy bumps, and third pads are each arranged in a second direction perpendicular to the first direction, and,
when a pitch between the second bumps adjacent to each other in the second direction is greater than 2A, a third dummy bump is provided between the second bumps, and third dummy bumps are arranged in the second direction between the first dummy bumps and between the second dummy bumps.

### Claim 6 (depends on 1)

The semiconductor package of claim 1, wherein no bump is provided on the first pad and the third pad.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the groove is a damage shape during a test for the interface chip or the at least one memory chip.

### Claim 8 (depends on 1)

The semiconductor package of claim 1, wherein the second pad is formed in an open structure and is electrically connected to the first bump, and
the fourth pad is formed in a closed structure and is not electrically connected to the dummy bump provided on the fourth pad.

### Claim 9 (depends on 1)

The semiconductor package of claim 1, wherein the interface chip and the at least one memory chip have substantially the same size,
the first pad and the third pad overlap each other, the second pad and the fourth pad overlap each other, and the first TSV and the second TSV are arranged in positions overlapping each other, and
the first TSV and the second TSV are electrically connected to each other through the second bump.

### Claim 10 (depends on 1)

The semiconductor package of claim 1, wherein the at least one memory chip includes a plurality of memory chips,
the memory chips of the at least one memory chip except for a lowermost memory chip are stacked on other memory chips corresponding thereto, and
the at least one memory chip is stacked on the interface chip or a corresponding memory chip via an adhesive layer by using a temperature-compression bonding (TCB) method.

### Claim 11

A semiconductor package comprising:
an interface chip comprising a first pad provided in an outer portion, and a second pad provided inside the first pad;
at least one memory chip, which is stacked on the interface chip and comprises a third pad provided in an outer portion, and a fourth pad provided inside the third pad; and
an adhesive layer provided between the interface chip and the at least one memory chip;
wherein the second pad is formed in an open structure, and the fourth pad is formed in a closed structure, and
each of the first pad and the third pad comprises a groove.

### Claim 12 (depends on 11)

The semiconductor package of claim 11, wherein a first bump is provided on the second pad on a bottom surface of the interface chip and is electrically connected to the second pad, and
a dummy bump is provided on the fourth pad on a bottom surface of the at least one memory chip and the dummy bump is not electrically connected to the fourth pad.

### Claim 13 (depends on 11)

The semiconductor package of claim 11, wherein the interface chip further comprises a first through silicon via (TSV) provided between the first pad and the second pad, and the at least one memory chip further comprises a second TSV provided between the third pad and the fourth pad,
the first TSV and the second TSV overlap each other,
a second bump is provided on the second TSV on a bottom surface of the at least one memory chip to electrically connect the first TSV to the second TSV through the second bump, and
a dummy bump is provided on a bottom surface of the at least one memory chip to be adjacent to the second bump.

### Claim 14 (depends on 11)

The semiconductor package of claim 11, wherein no bump is provided on the first pad and the third pad.

### Claim 15 (depends on 11)

The semiconductor package of claim 11, wherein the adhesive layer includes a non-conductive film (NCF) and has a structure protruding outward from side surfaces of the interface chip and the at least one memory chip.

### Claim 16

A semiconductor package comprising:
a printed circuit substrate (PCB);
an interface chip, which is stacked on the PCB and comprises a first pad provided in an outer portion, a second pad provided inside the first pad, and a first through silicon via (TSV) provided between the first pad and the second pad;
at least one memory chip, which is stacked on the interface chip and comprises a third pad provided in an outer portion, a fourth pad provided inside the third pad, and a second TSV provided between the third pad and the fourth pad;
an adhesive layer provided between the interface chip and the at least one memory chip; and
a sealant for sealing the interface chip and the at least one memory chip on the PCB,
wherein a first bump is provided on the second pad on a bottom surface of the interface chip, and
a second bump is provided on the second TSV on a bottom surface of the at least one memory chip and a first dummy bump is provided on the fourth pad on a bottom surface of the at least one memory chip.

### Claim 17 (depends on 16)

The semiconductor package of claim 16, wherein each of the first pad and the third pad comprises a groove, and
no bump is provided on the first pad and the third pad.

### Claim 18 (depends on 16)

The semiconductor package of claim 16, wherein a second dummy bump is provided on the bottom surface of the at least one memory chip between the third pad and the second bump, and,
when a minimum pitch between adjacent second TSVs or adjacent second bumps is denoted as A, a distance between the second bump and the first dummy bump or a second dummy bump is denoted as B, and a distance between the third pad and the second dummy bump is denoted as C, inequalities A≤B≤2 A and A≤C are satisfied.

### Claim 19 (depends on 18)

The semiconductor package of claim 18, wherein the adhesive layer includes a non-conductive film (NCF) and has a structure protruding outward from side surfaces of the interface chip and the at least one memory chip.

### Claim 20 (depends on 18)

The semiconductor package of claim 18, wherein the first dummy bump, the second bump, the second dummy bump, and a pad are arranged in an order stated in a first direction from a center of the at least one memory chip toward the outside,
first dummy bumps, second bumps, second dummy bumps, and pads are each arranged in a second direction perpendicular to the first direction, and,
when a pitch between the second bumps adjacent to each other in the second direction is greater than 2A, a third dummy bump is provided between the second bumps, and third dummy bumps are also arranged in the second direction between the first dummy bumps and between the second dummy bumps.