# US 12,119,328 B2 · Methods of fabricating the same die stack structure and semiconductor structure

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,119,328 B2
- Document ID: US12119328B2
- Status: Granted
- Kind: B2
- Application number: 18/362,973
- Filed: 2023-08-01
- Published: 2024-01-18
- Granted: 2024-10-15
- Earliest claimed: 2020-05-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Ming-Fa Chen; Chao-Wen Shih; Min-Chien Hsiao; Nien-Fang Wu; Sung-Feng Yeh; Tzuan-Horng Liu
- Web page: https://patentgrep.com/patent/US12119328B2

## CPC

- H10W 90/00: Package configurations
- H10D 62/117: {Shapes of semiconductor bodies}
- H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 72/74: {using temporarily an auxiliary support}
- H10P 72/7402: {Wafer tapes, e.g. grinding or dicing support tapes}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 72/0198: {batch processes}
- H10W 72/90: Bond pads, in general
- H10W 74/01: Manufacture or treatment
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 72/019: {of bond pads}
- H10W 72/075: {of bond wires}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/551: {Materials of bond wires}
- H10W 72/874: {On different surfaces}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/9413: {on encapsulations}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/951: {Materials of bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/963: {Providing mechanical bonding or support, e.g. dummy bond pads}
- H10W 72/967: {Multiple bond pads having different functions}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/014: {using batch processing}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/10: characterised by their shape or disposition
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 80/016: {Cleaning}
- H10W 80/102: {Controlling the environment during the bonding, e.g. the temperature or pressure}
- H10W 80/301: {Bonding techniques, e.g. hybrid bonding}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/20: Configurations of stacked chips
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A die stack structure including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a redistribution circuit structure is provided. The first semiconductor die includes a first semiconductor substrate including a first portion and a second portion, a first interconnect structure and a first bonding structure. The first interconnect structure is disposed on a top surface of the second portion, a lateral dimension of the first portion is greater than a lateral dimension of the top surface of the second portion. The second semiconductor die is disposed on the first semiconductor die and includes a second bonding structure, the second semiconductor die is electrically connected with the first semiconductor die through the first and second bonding structures. The insulating encapsulation is disposed on the first portion and laterally encapsulating the second portion and the second semiconductor die. The redistribution circuit structure is electrically connected with the first and second semiconductor dies, and the lateral dimension of the first portion is greater than a lateral dimension of the redistribution circuit structure.

## Claims

### Claim 1

A method for fabricating a die stack structure, comprising:
bonding a semiconductor die to a semiconductor wafer, the semiconductor wafer comprising a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate;
forming first grooves on portions of the semiconductor wafer uncovered by the semiconductor die, wherein the first grooves extend through the interconnect structure into the semiconductor substrate;
laterally encapsulating the semiconductor die and filling the first grooves with an insulating encapsulation;
forming a redistribution circuit structure on the semiconductor substrate, wherein the redistribution circuit structure and the semiconductor die are located at opposite sides of the semiconductor substrate;
forming second grooves, wherein the second grooves extend through the redistribution circuit structure into the semiconductor substrate; and
performing a wafer sawing process to saw the semiconductor wafer, wherein a maximum lateral dimension of the first grooves is wider than a maximum cutting width of the wafer sawing process.

### Claim 2 (depends on 1)

The method as claimed in claim 1, wherein the first grooves are formed through a first laser grooving process.

### Claim 3 (depends on 2)

The method as claimed in claim 2, wherein the wafer sawing process comprises a blade saw process, and a first cutting width of the first laser grooving process is wider than a second cutting width of the blade saw process.

### Claim 4 (depends on 3)

The method as claimed in claim 3, wherein before performing the wafer sawing process, the second grooves are formed on the semiconductor wafer through a second laser grooving process.

### Claim 5 (depends on 4)

The method as claimed in claim 4, wherein a third cutting width of the second laser grooving process is wider than the second cutting width of the blade saw process.

### Claim 6 (depends on 1)

The method as claimed in claim 1, wherein a maximum lateral dimension of the second grooves is wider than a maximum cutting width of the wafer sawing process.

### Claim 7 (depends on 1)

The method as claimed in claim 1, wherein the maximum lateral dimension of the first grooves is substantially the same as the maximum lateral dimension of second grooves.

### Claim 8

A method for fabricating a die stack structure, comprising:
bonding a semiconductor die to a first surface of a semiconductor wafer;
forming first grooves on the first surface of the semiconductor wafer, wherein a depth of the first grooves is smaller than a thickness of the semiconductor wafer;
forming an insulating encapsulation to encapsulate the semiconductor die and fill the first grooves;
forming a redistribution circuit structure on a second surface of the semiconductor wafer, wherein the first surface is opposite to the second surface;
forming second grooves, wherein the second grooves extend through the redistribution circuit structure; and
performing a wafer sawing process to saw the semiconductor wafer and insulating encapsulation.

### Claim 9 (depends on 8)

The method as claimed in claim 8, wherein a maximum lateral dimension of the first grooves is wider than a maximum cutting width of the wafer sawing process.

### Claim 10 (depends on 8)

The method as claimed in claim 8, wherein the first grooves are formed through a first laser grooving process.

### Claim 11 (depends on 10)

The method as claimed in claim 10, wherein the wafer sawing process comprises a blade saw process, and a first cutting width of the first laser grooving process is wider than a second cutting width of the blade saw process.

### Claim 12 (depends on 8)

The method as claimed in claim 8, wherein the second grooves are spaced apart from the first grooves.

### Claim 13 (depends on 8)

The method as claimed in claim 8, wherein the second grooves are formed to extend through the redistribution circuit structure into the semiconductor wafer.

### Claim 14 (depends on 8)

The method as claimed in claim 8, wherein a maximum lateral dimension of the first grooves is substantially the same as a maximum lateral dimension of.

### Claim 15 (depends on 8)

The method as claimed in claim 8, wherein a depth of the second grooves is smaller than a thickness of the semiconductor wafer.

### Claim 16

A method, comprising:
bonding top tier semiconductor dies to a semiconductor wafer comprising bottom tier semiconductor dies, each of the bottom tier semiconductor dies comprising a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate;
forming first grooves on the semiconductor wafer, the first grooves extending through the interconnect structures of the bottom tier semiconductor dies into the semiconductor substrates of the bottom tier semiconductor dies, and the semiconductor substrates of the bottom tier semiconductor dies being revealed by the first grooves;
forming an insulating encapsulation over the semiconductor wafer to laterally encapsulate the top tier semiconductor dies and fill the first grooves to form a reconstructed wafer;
forming a redistribution circuit structure on the reconstructed wafer to be electrically connected with the top tier semiconductor dies and the bottom tier semiconductor dies; and
performing a wafer sawing process to saw the reconstructed wafer along scribe lines of the semiconductor wafer to separate the bottom tier semiconductor dies, wherein a maximum lateral dimension of the first grooves is wider than a maximum cutting width of the wafer sawing process, each of the semiconductor substrates of the bottom tier semiconductor dies comprises a first portion and a second portion disposed on the first portion, each of the interconnect structures of the bottom tier semiconductor dies is disposed on a top surface of the corresponding second portion, a lateral dimension of the first portion is greater than a lateral dimension of the top surface of the second portion, the insulating encapsulation is located on the first portion and laterally encapsulating the second portion, and the lateral dimension of the first portion is greater than a lateral dimension of the redistribution circuit structure.

### Claim 17 (depends on 16)

The method as claimed in claim 16, wherein the first grooves are formed after bonding the top tier semiconductor dies to the semiconductor wafer, the first grooves are formed through a first laser grooving process performed along the scribe lines of the semiconductor wafer, the wafer sawing process comprises a blade saw process, and a first cutting width of the first laser grooving process is wider than a second cutting width of the blade saw process.

### Claim 18 (depends on 17)

The method as claimed in claim 17, wherein before performing the wafer sawing process, second grooves are formed on the reconstructed wafer through a second laser grooving process performed along the scribe lines of the semiconductor wafer, and a third cutting width of the second laser grooving process is wider than the second cutting width of the blade saw process.

### Claim 19 (depends on 18)

The method as claimed in claim 18, wherein the second grooves are formed to extend through the redistribution circuit structure into the insulating encapsulation, and the insulating encapsulation is revealed by the second grooves.

### Claim 20 (depends on 18)

The method as claimed in claim 18, wherein the second grooves are formed to extend through the redistribution circuit structure into the semiconductor substrates of the bottom tier semiconductor dies, and the semiconductor substrates of the bottom tier semiconductor dies are revealed by the second grooves.