# US 12,119,326 B2 · Microelectronic structures including bridges

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- Number: US 12,119,326 B2
- Document ID: US12119326B2
- Status: Granted
- Kind: B2
- Application number: 17/126,505
- Filed: 2020-12-18
- Published: 2022-06-23
- Granted: 2024-10-15
- Earliest claimed: 2020-12-18
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Omkar G. Karhade; Bohan Shan
- Web page: https://patentgrep.com/patent/US12119326B2

## CPC

- H10W 90/00: Package configurations
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 72/0198: {batch processes}
- H10W 74/01: Manufacture or treatment
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/63: Vias, e.g. via plugs
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 70/682: {comprising holes having chips therein}
- H10W 72/011: {Apparatus therefor}
- H10W 72/01223: {in liquid form, e.g. by dispensing droplets or by screen printing}
- H10W 72/01233: {in liquid form, e.g. spin coating, spray coating or immersion coating}
- H10W 72/01251: {Changing the shapes of bumps}
- H10W 72/01257: {by reflowing}
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/07223: {Active alignment, e.g. using optical alignment using marks or sensors}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/07252: {changes in structures or sizes}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/225: {Bumps having a filler embedded in a matrix}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/253: {not comprising solid metals or solid metalloids, e.g. polymers or ceramics}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/853: {On the same surface}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/9413: {on encapsulations}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

## Claims

### Claim 1

A microelectronic assembly, comprising:
a substrate; and
a microelectronic component coupled to the substrate by a solder interconnect, wherein the solder interconnect includes a first portion and a second portion, the first portion is between the second portion and the substrate, the first portion has a height between 20 microns and 50 microns, and the first portion has a ground top surface.

### Claim 2 (depends on 1)

The microelectronic assembly of claim 1, wherein the substrate includes an organic dielectric material.

### Claim 3 (depends on 1)

The microelectronic assembly of claim 1, further comprising:
a bridge component, wherein the microelectronic component is coupled to the bridge component by solder, the bridge component is coupled to the substrate by solder, and the bridge component is at least partially between the substrate and the microelectronic component.

### Claim 4

A microelectronic assembly, comprising:
a substrate;
a first microelectronic component coupled to the substrate by a first solder interconnect, wherein the first solder interconnect includes a first portion and a second portion, the first portion is between the second portion and the substrate, and the first portion has a ground top surface;
a bridge component, wherein the first microelectronic component is coupled to the bridge component by solder, the bridge component is coupled to the substrate by solder, and the bridge component is at least partially between the substrate and the first microelectronic component; and
a second microelectronic component coupled to the substrate by a second solder interconnect, wherein the second solder interconnect includes a first portion and a second portion, the first portion of the second solder interconnect is between the second portion of the second solder interconnect and the substrate, the first portion of the second solder interconnect has a ground top surface, the second microelectronic component is coupled to the bridge component by solder, and the bridge component is at least partially between the substrate and the second microelectronic component.

### Claim 5 (depends on 4)

The microelectronic assembly of claim 4, wherein the first portion of the second solder interconnect has a height between 20 microns and 50 microns.

### Claim 6 (depends on 4)

The microelectronic assembly of claim 4, wherein a top surface of the bridge component is coplanar with the ground top surface of the first portion of the first solder interconnect.

### Claim 7 (depends on 4)

The microelectronic assembly of claim 4, wherein the substrate includes an organic dielectric material.

### Claim 8

A microelectronic assembly, comprising:
a substrate;
a first microelectronic component coupled to the substrate by first solder interconnects, wherein individual first solder interconnects include a first portion and a second portion, and interfaces between the first portion and the second portion are coplanar across the first solder interconnects;
a bridge component, wherein the first microelectronic component is coupled to the bridge component by solder, the bridge component is coupled to the substrate by solder, and the bridge component is at least partially between the substrate and the first microelectronic component; and
a second microelectronic component coupled to the substrate by a second solder interconnect, wherein the second solder interconnect includes a first portion and a second portion, the first portion of the second solder interconnect is between the second portion of the second solder interconnect and the substrate, the first portion of the second solder interconnect has a ground top surface, the second microelectronic component is coupled to the bridge component by solder, and the bridge component is at least partially between the substrate and the second microelectronic component.

### Claim 9 (depends on 8)

The microelectronic assembly of claim 8, first portion of the individual first solder interconnects has a height between 20 microns and 50 microns.

### Claim 10 (depends on 8)

The microelectronic assembly of claim 8, wherein has a height between 20 microns and 50 microns.

### Claim 11 (depends on 8)

The microelectronic assembly of claim 8, wherein the bridge component is at least partially in a cavity in the substrate.

### Claim 12 (depends on 8)

The microelectronic assembly of claim 8, wherein a top surface of the bridge component is coplanar with the interfaces between the first portions and the second portions of the first solder interconnects.

### Claim 13 (depends on 8)

The microelectronic assembly of claim 8, wherein a top surface of the bridge component is non-coplanar with the interfaces between the first portions and the second portions of the first solder interconnects.

### Claim 14

A microelectronic assembly, comprising:
a substrate;
a first microelectronic component coupled to the substrate by a first interconnect, wherein the first interconnect includes a first portion and a second portion, the first portion includes solder, the first portion is between the second portion and the substrate, and the first portion has a ground top surface;
a bridge component, wherein the first microelectronic component is coupled to the bridge component by solder, the bridge component is coupled to the substrate by solder, and the bridge component is at least partially between the substrate and the first microelectronic component; and
a second microelectronic component coupled to the substrate by a second interconnect, wherein the second interconnect includes a first portion and a second portion, the first portion of the second interconnect includes solder, the first portion of the second interconnect is between the second portion of the second interconnect and the substrate, the first portion of the second interconnect has a ground top surface, the second microelectronic component is coupled to the bridge component by solder, and the bridge component is at least partially between the substrate and the second microelectronic component.

### Claim 15 (depends on 14)

The microelectronic assembly of claim 14,
wherein the bridge component includes a transistor.

### Claim 16 (depends on 14)

The microelectronic assembly of claim 14, wherein the bridge component does not include a transistor.

### Claim 17 (depends on 14)

The microelectronic assembly of claim 14, wherein the bridge component is at least partially in a cavity in the substrate.

### Claim 18 (depends on 14)

The microelectronic assembly of claim 14, wherein a top surface of the bridge component is coplanar with the ground top surface of the first portion of the first interconnect.

### Claim 19 (depends on 14)

The microelectronic assembly of claim 14, wherein a top surface of the bridge component is non-coplanar with the ground top surface of the first portion of the first interconnect.

### Claim 20 (depends on 14)

The microelectronic assembly of claim 14, wherein the substrate includes an organic dielectric material.