# US 12,119,325 B2 · Semiconductor device assemblies with molded support substrates

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- Number: US 12,119,325 B2
- Document ID: US12119325B2
- Status: Granted
- Kind: B2
- Application number: 17/224,234
- Filed: 2021-04-07
- Published: 2021-07-22
- Granted: 2024-10-15
- Earliest claimed: 2017-04-06
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Mitsuhisa Watanabe; Fumitomo Watanabe; Masanori Yoshida
- Web page: https://patentgrep.com/patent/US12119325B2

## CPC

- H10W 90/00: Package configurations
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 72/0198: {batch processes}
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 72/072: {of bump connectors}
- H10W 72/07254: {changes in dispositions}
- H10W 72/073: {of die-attach connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/9413: {on encapsulations}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/20: Configurations of stacked chips
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor device assemblies with molded support substrates and associated methods are disclosed herein. In one embodiment, a semiconductor device assembly includes a support substrate, a first semiconductor die embedded within the support substrate, a second semiconductor die coupled to the support substrate, and a third semiconductor die coupled to the support substrate. The assembly can also include a redistribution network formed on a first and/or second side of the support substrate, and a plurality of conductive contacts electrically coupled to at least one of the first, second or third semiconductor dies.

## Claims

### Claim 1

A semiconductor device assembly, comprising:
a support substrate having a bottom surface;
a first semiconductor die at least partially embedded within the support substrate and configured to route signals across a thickness of the support substrate, wherein the first semiconductor die includes:
a die top surface with a top contact thereon, the top contact for coupling to circuits external to the first semiconductor die, and
a die bottom surface embedded within the support substrate and located over a bottom surface of the support substrate;
at least one interconnect extending partially through the support substrate and between the die bottom surface and the bottom surface of the support substrate;
a second semiconductor die attached to the support substrate;
a die stack attached to the support substrate; and
a plurality of conductive contacts attached to the support substrate opposite the second semiconductor die, wherein a portion of the conductive contacts are electrically coupled to the second semiconductor die and/or one or more dies in the die stack through the first semiconductor die.

### Claim 2 (depends on 1)

The semiconductor device assembly of claim 1 wherein the support substrate comprises a first mold material, and wherein the semiconductor device assembly further comprises a second mold material at least partially encapsulating the second semiconductor die and/or the die stack.

### Claim 3 (depends on 1)

The semiconductor device assembly of claim 1, wherein:
the first semiconductor die includes the die top surface embedded within the support substrate and located below a top surface of the support substrate; and
further comprising:
at least one interconnect extending partially through the support substrate and between the die top surface and the top surface of the support substrate, the least one interconnect directly connected to the top contact of the first semiconductor die.

### Claim 4 (depends on 1)

The semiconductor device assembly of claim 1 wherein the support substrate comprises a molded material, and wherein the first semiconductor die has a backside, an active side opposite the backside, and a sidewall between the active side and the backside, and wherein the backside, active side and the sidewall are fully encapsulated within the molded material.

### Claim 5 (depends on 1)

The semiconductor device assembly of claim 1, wherein the first semiconductor die is configured to route at least one signal between the plurality of conductive contacts located across the thickness of the support substrate, wherein the plurality of conductive contacts is further offset along a direction orthogonal to the thickness of the support substrate.

### Claim 6 (depends on 1)

The semiconductor device assembly of claim 1 wherein the first semiconductor die includes a communication component, the second semiconductor die includes a controller, and the die stack includes a memory circuit.

### Claim 7 (depends on 1)

The semiconductor device assembly of claim 1 wherein the support substrate further comprises a first mounting region and a second mounting region spaced apart from the first mounting region, and wherein:
the second semiconductor die is mounted to the first mounting region; and
the first semiconductor die is below the second mounting region;
the semiconductor device assembly further comprising:
a third semiconductor die mounted to the second mounting region.

### Claim 8 (depends on 1)

The semiconductor device assembly of claim 1 wherein the support substrate includes an epoxy resin that at least partially encapsulates the first semiconductor die.

### Claim 9

A semiconductor device assembly, comprising:
a support structure having a mounting surface and a bottom portion;
a stack of memory dies attached to the mounting surface;
a logic die electrically coupled to the stack of memory dies;
an intermediary die at least partially embedded within the support structure and electrically coupled to at least one of the logic die or the stack of memory dies,
wherein the intermediary die is configured to route signals at least partially across a thickness of the support substrate, and
wherein the intermediary die includes (1) a die top surface with a top contact thereon, the top contact for coupling to circuits external to the intermediary die and (2) a bottom surface; and
at least one interconnect extending between the bottom portion of the support structure and the bottom surface of the intermediary die.

### Claim 10 (depends on 9)

The semiconductor device assembly of claim 9, wherein the at least one interconnect is for electrically coupling the intermediary die to the logic die, the stack of memory dies, or both.

### Claim 11 (depends on 10)

The semiconductor device assembly of claim 10 wherein the one or more interconnects extend between a top portion of the support structure and a top surface of the intermediary die.

### Claim 12 (depends on 9)

The semiconductor device assembly of claim 9 wherein the support structure further comprises a redistribution network extending over intermediary die.

### Claim 13 (depends on 12)

The semiconductor device assembly of claim 12 wherein the redistribution network includes one or more conductive contacts electrically coupled to the intermediary die.

### Claim 14 (depends on 9)

The semiconductor device assembly of claim 9 wherein the mounting surface includes a first region and a second region spaced apart from the first region, wherein the logic die is disposed above the first region, the stack of memory dies is disposed above the second region, and the intermediary die is disposed below the second region.

### Claim 15 (depends on 9)

The semiconductor device assembly of claim 9 wherein the intermediary die is configured to route at least one electrical signal between contacts that are located across the thickness of the support substrate and offset along a direction orthogonal to the thickness.

### Claim 16

A semiconductor device assembly, comprising:
a support structure having a mounting surface and a cavity;
a stack of memory dies attached to the mounting surface;
a logic die mounted to the mounting surface and encapsulated by a first mold material, wherein the logic die is electrically coupled to the stack of memory dies;
an intermediary die at least partially embedded within the cavity of the support structure and electrically coupled to at least one of the logic die or the stack of memory dies,
wherein the intermediary die is configured to route signals at least partially across a thickness of the support substrate,
wherein the intermediary die includes (1) a die top surface with a top contact thereon, the top contact for coupling to circuits external to the intermediary die,
a second mold material in the cavity of the support structure and encapsulating the intermediary die.

### Claim 17 (depends on 16)

The semiconductor device assembly of claim 16 wherein the intermediary die is fully encapsulated within a mold material included in the support structure.

### Claim 18 (depends on 17)

The semiconductor device assembly of claim 17 wherein the mold material is an epoxy resin.