# US 12,119,324 B2 · Package structure

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- Number: US 12,119,324 B2
- Document ID: US12119324B2
- Status: Granted
- Kind: B2
- Application number: 17/963,181
- Filed: 2022-10-10
- Published: 2023-02-02
- Granted: 2024-10-15
- Earliest claimed: 2019-12-25
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Kung-Chen Yeh; Szu-Wei Lu; Tsung-Fu Tsai; Ying-Ching Shih
- Web page: https://patentgrep.com/patent/US12119324B2

## CPC

- H10P 72/74: {using temporarily an auxiliary support}
- H10W 72/0198: {batch processes}
- H10P 34/42: with electromagnetic radiation, e.g. laser annealing (laser cutting H10P54/20)
- H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 74/014: {using batch processing}
- H10W 74/141: {the encapsulations being on at least the sidewalls of the semiconductor body}
- H10W 90/00: Package configurations
- H10P 72/7418: {of passive members, e.g. a chip mounting substrate}
- H10W 72/072: {of bump connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A package structure including an interposer, at least one semiconductor die and an insulating encapsulation is provided. The interposer includes a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, the interconnect structure includes interlayer dielectric films and interconnect wirings embedded in the interlayer dielectric films, the semiconductor substrate includes a first portion and a second portion disposed on the first portion, the first interconnect structure is disposed on the second portion, and a first maximum lateral dimension of the first portion is greater than a second maximum lateral dimension of the second portion. The at least one semiconductor die is disposed over and electrically connected to the interconnect structure. The insulating encapsulation is disposed on the first portion, wherein the insulating encapsulation laterally encapsulates the least one semiconductor die and the second portion.

## Claims

### Claim 1

A package structure, comprising:
an interposer, comprising:
a semiconductor substrate comprising a first bulk portion and a second bulk portion disposed on the first bulk portion; and
an interconnect structure disposed on the second bulk portion, wherein a first sub-portion of the second bulk portion comprises first sidewalls, a second sub-portion of the second bulk portion comprises second sidewalls, and the first sidewalls and second sidewalls are different in slope, wherein the first sidewalls substantially linearly extend from a top surface of the semiconductor substrate to the second sidewalls, and the second sidewalls are substantially perpendicular to the top surface of the semiconductor substrate;
at least one semiconductor die disposed over and electrically connected to the interconnect structure; and
an insulating encapsulation disposed on the interposer and laterally encapsulating the least one semiconductor die.

### Claim 2 (depends on 1)

The structure as claimed in claim 1, wherein the insulating encapsulation is in contact with sidewalls of the interconnect structure, the first sidewalls of the first sub-portion and the second sidewalls of the second sub-portion, and outer sidewalls of the insulating encapsulation are substantially aligned with sidewalls of the first bulk portion.

### Claim 3 (depends on 1)

The structure as claimed in claim 1, wherein the insulating encapsulation comprises a body portion and a ring portion, the body portion laterally encapsulates the at least one semiconductor die, and the ring portion is in contact with sidewalls of the interconnect structure, the first sidewalls of the first sub-portion and the second sidewalls of the second sub-portion.

### Claim 4 (depends on 1)

The structure as claimed in claim 1, wherein the at least one semiconductor die is electrically connected to the interposer through bump joints.

### Claim 5 (depends on 4)

The structure as claimed in claim 4 further comprising:
a first underfill disposed between the at least one semiconductor die and the second bulk portion of the interposer, wherein the first underfill encapsulates the bump joints, and the bump joints are spaced apart from the insulating encapsulation by the first underfill.

### Claim 6 (depends on 1)

The structure as claimed in claim 1, wherein sidewalls of the interconnect structure and the first sidewalls of the first sub-portion are substantially equal in slope.

### Claim 7 (depends on 6)

The structure as claimed in claim 6 further comprising:
a circuit substrate;
first conductive terminals disposed on and electrically connected to the circuit substrate;
second conductive terminals disposed on and electrically connected to the circuit substrate, wherein the interposer is electrically connected to the circuit substrate through the first conductive terminals, and the first conductive terminals and the second conductive terminals are disposed on opposite sides of the circuit substrate; and
a second underfill disposed between the interposer and the circuit substrate, wherein the second underfill encapsulates the first conductive terminals.

### Claim 8

A package structure, comprising:
an interposer comprising a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate;
at least one semiconductor die disposed over and electrically connected to the interconnect structure; and
an insulating encapsulation disposed on the interposer, wherein the insulating encapsulation encapsulates the least one semiconductor die and comprises a body portion and a ring portion, the body portion laterally encapsulates the at least one semiconductor die, the ring portion comprises a first ring portion and a second ring portion, wherein the first ring portion is between the second ring portion and the body portion, and a first interface is between the first ring portion and the interposer, a second interface is between the second ring portion and the interposer, and an obtuse included angle is between the first interface and the second interface, wherein the first interface has a substantially constant angle with respect to a top surface of the semiconductor substrate.

### Claim 9 (depends on 8)

The structure as claimed in claim 8, wherein a maximum width of the first ring portion is wider than a maximum width of the second ring portion.

### Claim 10 (depends on 8)

The structure as claimed in claim 8, wherein a minimum width of the first ring portion is substantially equal to a maximum width of the second ring portion.

### Claim 11 (depends on 8)

The structure as claimed in claim 8, wherein a minimum width of the first ring portion is wider than a minimum width of the second ring portion.

### Claim 12 (depends on 8)

The structure as claimed in claim 8, wherein the at least one semiconductor die is electrically connected to the interposer through bump joints.

### Claim 13 (depends on 12)

The structure as claimed in claim 12 further comprising:
a first underfill disposed between the at least one semiconductor die and the interposer, wherein the first underfill encapsulates the bump joints, and the bump joints are spaced apart from the insulating encapsulation by the first underfill.

### Claim 14 (depends on 8)

The structure as claimed in claim 8 further comprising:
a circuit substrate;
first conductive terminals disposed on and electrically connected to the circuit substrate;
second conductive terminals disposed on and electrically connected to the circuit substrate, wherein through semiconductor vias of the interposer are electrically connected to the circuit substrate through the first conductive terminals, and the first conductive terminals and the second conductive terminals are disposed on opposite sides of the circuit substrate; and
a second underfill disposed between the interposer and the circuit substrate, wherein the second underfill encapsulates the first conductive terminals.

### Claim 15

A package structure, comprising:
an interposer comprising a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, wherein the semiconductor substrate comprises a first bulk portion and a second bulk portion, the second bulk portion is between the first bulk portion and the interconnect structure, first tapered sidewalls of the interconnect structure and second tapered sidewalls of a first sub-portion of the second bulk portion are substantially equal in slope, the second tapered sidewalls of the first sub-portion of the second bulk portion and sidewalls of a second sub-portion of the second bulk portion are different in slope, wherein the second tapered sidewalls of the first sub-portion of the second bulk portion substantially linearly extends from a top surface of the semiconductor substrate to the sidewalls of the second sub-portion of the second bulk portion, and the sidewalls of the second sub-portion of the second bulk portion are substantially perpendicular to the top surface of the semiconductor substrate;
at least one semiconductor die disposed over and electrically connected to the interconnect structure; and
an insulating encapsulation disposed on the interposer and encapsulating the least one semiconductor die.

### Claim 16 (depends on 15)

The structure as claimed in claim 15, wherein a portion of the first bulk portion is uncovered by the second bulk portion, and the portion of the first bulk portion uncovered by the second bulk portion is covered and in contact with the insulating encapsulation.

### Claim 17 (depends on 15)

The structure as claimed in claim 15, wherein the insulating encapsulation comprises a body portion and a ring portion, the body portion laterally encapsulates the at least one semiconductor die, the ring portion covers the first tapered sidewalls of the interconnect structure, the second tapered sidewalls of the first sub-portion of the second bulk portion as well as the sidewalls of the second sub-portion of the second bulk portion.

### Claim 18 (depends on 15)

The structure as claimed in claim 15, wherein the at least one semiconductor die is electrically connected to the interposer through bump joints.

### Claim 19 (depends on 18)

The structure as claimed in claim 18 further comprising:
a first underfill disposed between the at least one semiconductor die and the interposer, wherein the first underfill encapsulates the bump joints, and the bump joints are spaced apart from the insulating encapsulation by the first underfill.

### Claim 20 (depends on 15)

The structure as claimed in claim 15, wherein the second tapered sidewalls of the second sub-portion of the second bulk portion comprises a curved sidewall.