# US 12,119,323 B2 · Semiconductor device and method of manufacturing semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,119,323 B2 - Document ID: US12119323B2 - Status: Granted - Kind: B2 - Application number: 17/944,018 - Filed: 2022-09-13 - Published: 2023-01-05 - Granted: 2024-10-15 - Earliest claimed: 2020-07-20 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Soichi Homma - Web page: https://patentgrep.com/patent/US12119323B2 ## CPC - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 90/00: Package configurations - H10W 72/01271: {Cleaning, e.g. oxide removal or de-smearing} - H10W 72/07141: {Means for applying energy, e.g. ovens or lasers} - H10W 72/072: {of bump connectors} - H10W 72/07207: {Temporary substrates, e.g. removable substrates} - H10W 72/07211: {Treating the bond pad before connecting, e.g. by applying flux or cleaning} - H10W 72/07221: {Aligning} - H10W 72/07232: {Compression bonding, e.g. thermocompression bonding} - H10W 72/07235: {Applying EM radiation, e.g. induction heating or using a laser} - H10W 72/07236: {Soldering or alloying} - H10W 72/07254: {changes in dispositions} - H10W 72/073: {of die-attach connectors} - H10W 72/07327: {involving guiding structures, e.g. spacers or supporting members} - H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/242: {relative to the surface, e.g. recessed, protruding} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/865: {Die-attach connectors and bond wires} - H10W 72/877: {Bump connectors and die-attach connectors} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/231: {the stacked chips being on both top and bottom sides of an auxiliary carrier having no electrical connection structure} - H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape - H10W 90/271: {the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement} - H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/732: {between stacked chips} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/752: {between stacked chips} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract According to one embodiment, a method of manufacturing a semiconductor device includes forming a metal bump on a first surface side of a semiconductor chip, positioning the semiconductor chip so the metal bump contacts a pad of an interconnection substrate, and applying a first light from a second surface side of the semiconductor chip and melting the metal bump with the first light. After the melting, the melted metal bump is allowed to resolidify by stopping or reducing the application of the first light. The semiconductor chip is then pressed toward the interconnection substrate. A second light is then applied from the second surface side of the semiconductor chip while the semiconductor chip is being pressed toward the interconnection substrate to melt the metal bump. After the melting, the melted metal bump is allowed to resolidify by the stopping or reducing of the application of the second light. ## Claims ### Claim 1 A method of manufacturing a semiconductor device, the method comprising: forming a metal bump on a first surface side of a semiconductor chip; positioning the semiconductor chip so the metal bump contacts a pad of an interconnection substrate; applying a first light from a second surface side of the semiconductor chip and melting the metal bump with the first light; allowing the melted metal bump to resolidify by stopping or reducing the application of the first light; pressing the semiconductor chip toward the interconnection substrate after the stopping or reducing of the application of the first light; applying a second light from the second surface side of the semiconductor chip while pressing the semiconductor chip toward the interconnection substrate to melt the metal bump; and allowing the melted metal bump to resolidify by stopping or reducing the application of the second light, wherein the application of the second light is started after the pressing of the semiconductor chip toward the interconnection substrate begins, and the pressing of the semiconductor chip toward the interconnection substrate is stopped after the stopping or reducing of the application of the second light. ### Claim 2 (depends on 1) The method according to claim 1, wherein a flux is applied to at least one of the pad or the metal bump before the positioning of semiconductor chip. ### Claim 3 (depends on 1) The method according to claim 1, wherein a wavelength of the first light is in a range of 850 nm to 1100 nm, and a wavelength of the second light is in a range of 850 nm to 1100 nm. ### Claim 4 (depends on 1) The method according to claim 1, wherein an intensity of the second light is higher than an intensity of the first light. ### Claim 5 (depends on 1) The method according to claim 1, wherein a first mask is disposed on the semiconductor chip side of the interconnection substrate, the first mask covering, when viewed in a plan view, at least a portion of the interconnection substrate not overlapped by the semiconductor chip, and the application of the first light is performed through the first mask. ### Claim 6 (depends on 5) The method according to claim 5, wherein a second mask is disposed on the semiconductor chip side of the interconnection substrate, the second mask covering, when viewed in a plan view, at least a portion of the interconnection substrate not overlapped by the semiconductor chip, and the application of the second light is performed through the second mask. ### Claim 7 (depends on 6) The method according to claim 6, wherein the first mask and the second mask are on the second surface side of the semiconductor chip. ### Claim 8 (depends on 6) The method according to claim 6, wherein the first mask and the second mask are arranged on the interconnection substrate side of the semiconductor chip. ### Claim 9 (depends on 1) The method according to claim 1, wherein a mask is disposed on the semiconductor chip side of the interconnection substrate, the mask covering, when viewed in a plan view, at least a portion of the interconnection substrate not overlapped by the semiconductor chip, and the application of the first or second light is performed through the mask. ### Claim 10 (depends on 1) The method according to claim 1, wherein, when the semiconductor chip is pressed toward the interconnection substrate, a position of the semiconductor chip that moves with the pressurization is held. ### Claim 11 A method of manufacturing a semiconductor device, the method comprising: forming a plurality of metal bumps on a first surface side of a semiconductor chip; positioning the semiconductor chip so the plurality of metal bumps correspond in planar position to a plurality of pads of an interconnection substrate; bringing at least some of the metal bumps into contact with corresponding ones of the plurality of pads; applying a first light from a second surface side of the semiconductor chip and melting at least some of the metal bumps with the first light; allowing the melted metal bumps to resolidify by stopping or reducing the application of the first light; pressing the semiconductor chip toward the interconnection substrate after the stopping or reducing of the application of the first light to additionally cause one or more metal bumps to come in contact with a corresponding one of the pads; applying a second light from the second surface side of the semiconductor chip while pressing the semiconductor chip toward the interconnection substrate to melt at least some of the metal bumps; and allowing the melted metal bumps to resolidify by stopping or reducing the application of the second light, wherein the pressing of the semiconductor chip toward the interconnection substrate corrects a warping of the semiconductor chip. ### Claim 12 A method of manufacturing a semiconductor device, the method comprising: forming a metal bump on a first surface side of a semiconductor chip; positioning the semiconductor chip so the metal bump contacts a pad of an interconnection substrate; applying a first light from a second surface side of the semiconductor chip and melting the metal bump with the first light without pressing the semiconductor chip toward the interconnection substrate; allowing the melted metal bump to resolidify by stopping or reducing the application of the first light; pressing the semiconductor chip toward the interconnection substrate after the stopping or reducing of the application of the first light; applying a second light from the second surface side of the semiconductor chip while pressing the semiconductor chip toward the interconnection substrate to melt the metal bump; and allowing the melted metal bump to resolidify by stopping or reducing the application of the second light. ### Claim 13 (depends on 12) The method according to claim 12, wherein, in the applying of the first light, the entire surface of the semiconductor chip that is exposed to the first light is exposed at the same time. ### Claim 14 (depends on 12) The method according to claim 12, wherein the application of the second light is stopped or reduced when the pressing is stopped. ### Claim 15 (depends on 12) The method according to claim 12, wherein the application of the second light is performed while the semiconductor chip is being pressed into contact with the interconnection substrate, and the pressing is stopped when the application of the second light is stopped or reduced. ### Claim 16 (depends on 12) The method according to claim 12, wherein the application of the second light is started after the pressing of the semiconductor chip toward the interconnection substrate begins, and the pressing of the semiconductor chip toward the interconnection substrate is stopped after the stopping or reducing of the application of the second light. ### Claim 17 (depends on 12) The method according to claim 12, wherein a flux is applied to at least one of the pad or the metal bump before the positioning of semiconductor chip. ### Claim 18 (depends on 12) The method according to claim 12, wherein a wavelength of the first light is in a range of 850 nm to 1100 nm, and a wavelength of the second light is in a range of 850 nm to 1100 nm. ### Claim 19 (depends on 12) The method according to claim 12, wherein an intensity of the second light is higher than an intensity of the first light. ### Claim 20 (depends on 12) The method according to claim 12, wherein a first mask is disposed on the semiconductor chip side of the interconnection substrate, the first mask covering, when viewed in a plan view, at least a portion of the interconnection substrate not overlapped by the semiconductor chip, and the application of the first light is performed through the first mask.