# US 12,119,320 B2 · Chip package structure with bump

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- Number: US 12,119,320 B2
- Document ID: US12119320B2
- Status: Granted
- Kind: B2
- Application number: 17/869,118
- Filed: 2022-07-20
- Published: 2022-11-10
- Granted: 2024-10-15
- Earliest claimed: 2016-09-19
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Wei-Yu Chen; Li-Hsien Huang; An-Jhih Su; Hsien-Wei Chen
- Web page: https://patentgrep.com/patent/US12119320B2

## CPC

- H10W 74/014: {using batch processing}
- H10W 90/00: Package configurations
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/095: {of vias therein}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/635: {Through-vias}
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/0198: {batch processes}
- H10W 74/016: {using moulds}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 76/05: Providing fillings in containers, e.g. gas filling
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/01257: {by reflowing}
- H10W 72/072: {of bump connectors}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/07252: {changes in structures or sizes}
- H10W 72/07254: {changes in dispositions}
- H10W 72/073: {of die-attach connectors}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/354: {comprising polymers}
- H10W 72/874: {On different surfaces}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/9413: {on encapsulations}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/721: {of bump connectors}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A chip package structure is provided. The chip package structure includes a redistribution structure and a first chip structure over the redistribution structure. The chip package structure also includes a first solder bump between the redistribution structure and the first chip structure and a first molding layer surrounding the first chip structure. The chip package structure further includes a second chip structure over the first chip structure and a second molding layer surrounding the second chip structure. In addition, the chip package structure includes a third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump. A portion of the third molding layer is between the first molding layer and the redistribution structure.

## Claims

### Claim 1

A method for forming a chip package structure, the method comprising:
forming a first encapsulant along sidewalls of a first chip structure and a second chip structure;
forming one or more insulating layers over the first encapsulant the first chip structure, and the second chip structure;
attaching a third chip structure to the one or more insulating layers;
forming a first through via over the one or more insulating layers;
forming a second encapsulant over the one or more insulating layers, the second encapsulant extending along sidewalls of the third chip structure and the first through via; and
forming a third encapsulant along sidewalls of the first encapsulant, the one or more insulating layers, and the second encapsulant.

### Claim 2 (depends on 1)

The method of claim 1, wherein first contact pads of the third chip structure face away from the first chip structure.

### Claim 3 (depends on 2)

The method of claim 2, further comprising bonding the first contact pads of the third chip structure directly to a substrate.

### Claim 4 (depends on 3)

The method of claim 3, wherein bonding the first contact pads of the third chip structure is performed prior to forming the third encapsulant.

### Claim 5 (depends on 4)

The method of claim 4, wherein forming the first through via comprises forming the first through via through the one or more insulating layers to a second contact pad of the first chip structure.

### Claim 6 (depends on 4)

The method of claim 4 wherein the third encapsulant extends between the third chip structure and the substrate.

### Claim 7

A method for forming a chip package structure, the method comprising:
forming a first encapsulant along sidewalls of one or more first chip structures;
forming a first interconnect structure over the first encapsulant and the one or more first chip structures;
attaching a second chip structure to the first interconnect structure;
forming a through via over the first interconnect structure;
forming a second encapsulant along sidewalls of the second chip structure and the through via; and
forming a third encapsulant along sidewalls of the first encapsulant and the second encapsulant.

### Claim 8 (depends on 7)

The method of claim 7, wherein major surfaces of the one or more first chip structures are free of the first encapsulant and the second encapsulant.

### Claim 9 (depends on 7)

The method of claim 7, further comprising, prior to forming the third encapsulant, forming a second interconnect structure over the second chip structure, the through via, and the second encapsulant.

### Claim 10 (depends on 9)

The method of claim 9, wherein the first interconnect structure comprises a first via, wherein a width of the first via decreases as the first via extends away from the one or more first chip structures.

### Claim 11 (depends on 10)

The method of claim 10, wherein the second interconnect structure comprise a second via, wherein a width of the second via decreases as the second via extends away from the second chip structure.

### Claim 12 (depends on 7)

The method of claim 7, wherein the third encapsulant contacts a sidewall and a bottom of the second encapsulant.

### Claim 13

A method for forming a chip package structure, the method comprising:
forming a first encapsulant along sidewalls of a first chip structure;
forming one or more insulating layers over the first encapsulant and the first chip structure;
attaching a second chip structure to the one or more insulating layers;
forming a first through via over the one or more insulating layers;
forming a second encapsulant over the one or more insulating layers, the second encapsulant extending along sidewalls of the second chip structure, wherein forming the second encapsulant comprises forming the second encapsulant along sidewalls of the first through via; and
forming a third encapsulant along sidewalls of the first encapsulant, the one or more insulating layers, and the second encapsulant.

### Claim 14 (depends on 13)

The method of claim 13, further comprising, prior to forming the third encapsulant, bonding the second chip structure to a substrate.

### Claim 15 (depends on 14)

The method of claim 14, wherein forming the third encapsulant comprises forming the third encapsulant between the second chip structure and the substrate.

### Claim 16 (depends on 14)

The method of claim 14, further comprising:
forming conductive redistribution lines in the one or more insulating layers, wherein contact pads of the first chip structure are electrically coupled to corresponding ones of the conductive redistribution lines; and
forming a redistribution structure over the second chip structure and the second encapsulant prior to forming the third encapsulant.

### Claim 17 (depends on 16)

The method of claim 16, wherein forming the third encapsulant comprises forming the third encapsulant along sidewalls of the redistribution structure.

### Claim 18 (depends on 17)

The method of claim 17, wherein the first through via extends through the one or more insulating layers.

### Claim 19 (depends on 13)

The method of claim 13, wherein, after forming the third encapsulant, lateral edges of the first encapsulant are aligned with lateral edges of the second encapsulant.

### Claim 20 (depends on 18)

The method of claim 18, wherein a width of the first through via in the one or more insulating layers is less than a width of the first through via in the second encapsulant.