# US 12,119,318 B2 · Bonding structure and method of forming same

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- Number: US 12,119,318 B2
- Document ID: US12119318B2
- Status: Granted
- Kind: B2
- Application number: 18/303,302
- Filed: 2023-04-19
- Published: 2023-08-10
- Granted: 2024-10-15
- Earliest claimed: 2019-08-23
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Hsien-Wei Chen; Jie Chen; Ming-Fa Chen
- Web page: https://patentgrep.com/patent/US12119318B2

## CPC

- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 72/90: Bond pads, in general
- H10P 10/128: {by direct semiconductor to semiconductor bonding}
- H10W 20/042: {the barrier, adhesion or liner layers being seed or nucleation layers}
- H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/084: {for dual-damascene structures}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 72/019: {of bond pads}
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 90/00: Package configurations
- H10H 20/018: {Bonding of wafers}
- H10W 40/255: {having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/0198: {batch processes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/874: {On different surfaces}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/921: {Structures or relative sizes of bond pads}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/9413: {on encapsulations}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/963: {Providing mechanical bonding or support, e.g. dummy bond pads}
- H10W 72/967: {Multiple bond pads having different functions}
- H10W 80/016: {Cleaning}
- H10W 80/102: {Controlling the environment during the bonding, e.g. the temperature or pressure}
- H10W 80/301: {Bonding techniques, e.g. hybrid bonding}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 80/333: {Compression bonding}
- H10W 80/701: {characterised by the pads after the direct bonding}
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/722: {between stacked chips}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS

## Abstract

A device includes an interconnect structure over a substrate, multiple first conductive pads over and connected to the interconnect structure, a planarization stop layer extending over the sidewalls and top surfaces of the first conductive pads of the multiple first conductive pads, a surface dielectric layer extending over the planarization stop layer, and multiple first bonding pads within the surface dielectric layer and connected to the multiple first conductive pads.

## Claims

### Claim 1

A method comprising:
forming a first insulating layer over an interconnect structure, wherein the interconnect structure comprises a first conductive line and a second conductive line;
forming a conductive element over the first insulating layer and penetrating the first insulating layer to physically contact a first conductive line;
forming a first stop layer that extends conformally on surfaces of the first insulating layer and the conductive element;
forming a second insulating layer on the first stop layer, wherein the second insulating layer laterally surrounds the first conductive feature;
forming a second stop layer over the first stop layer and the second insulating layer;
forming a bonding layer on the second stop layer;
forming a first bonding pad penetrating the bonding layer, the second stop layer, and the first stop layer to physically contact the conductive element; and
forming a second bonding pad penetrating the bonding layer, the second stop layer, the second insulating layer, the first stop layer, and the first insulating layer to physically contact the second conductive line.

### Claim 2 (depends on 1)

The method of claim 1, wherein the second bonding pad has a first width within the bonding layer that is greater than a second width within the second insulating layer.

### Claim 3 (depends on 1)

The method of claim 1, wherein the second conductive line is electrically isolated from the rest of the interconnect structure.

### Claim 4 (depends on 1)

The method of claim 1 further comprising thinning upper portions of the first stop layer using a planarization process.

### Claim 5 (depends on 4)

The method of claim 4, wherein after performing the planarization process, top surfaces of the second insulating layer and the first stop layer are level.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first stop layer is a different material than the second stop layer.

### Claim 7 (depends on 1)

The method of claim 1, wherein forming the second bonding pad comprises:
forming an opening extending through the bonding layer and the second stop layer using a first etching process;
extending the opening through the second insulating layer, the first stop layer, and the first insulating layer using a second etching process; and
filling the opening with a conductive material.

### Claim 8 (depends on 7)

The method of claim 7, wherein the first etching process exposes the conductive element.

### Claim 9

A method comprising:
forming a first semiconductor device, comprising:
depositing a first stop layer on a first conductive pad;
depositing a first insulating layer on the first stop layer;
depositing a second stop layer on the first stop layer and the first insulating layer;
forming a first bonding layer on the second stop layer; and
forming a first bonding pad penetrating the first bonding layer to contact the first conductive pad;
forming a second semiconductor device, comprising:
depositing a third stop layer on a second conductive pad;
depositing a second insulating layer on the third stop layer;
depositing a fourth stop layer on the third stop layer and the second insulating layer;
forming a second bonding layer on the fourth stop layer; and
forming a second bonding pad penetrating the second bonding layer to contact the second conductive pad; and
bonding the first bonding layer to the second bonding layer and bonding the first bonding pad to the second bonding pad.

### Claim 10 (depends on 9)

The method of claim 9 further comprising bonding a third semiconductor device to the first semiconductor device.

### Claim 11 (depends on 9)

The method of claim 9, wherein forming the second semiconductor device further comprises forming a third bonding pad penetrating the second bonding layer, wherein the third bonding pad is a dummy bonding pad.

### Claim 12 (depends on 9)

The method of claim 9, wherein a width of the first semiconductor device is different from a width of the second semiconductor device.

### Claim 13 (depends on 9)

The method of claim 9 further comprising encapsulating the first semiconductor device and the second semiconductor device with an encapsulant.

### Claim 14 (depends on 13)

The method of claim 13 further comprising forming a redistribution structure on the first semiconductor device and the encapsulant.

### Claim 15 (depends on 9)

The method of claim 9, wherein a distance from the first conductive pad to the second conductive pad is in the range of 1 μm to 16 μm.

### Claim 16

A device comprising:
a first conductive element on a top surface of an interconnect structure, wherein the first conductive element is electrically connected to the interconnect structure;
a second conductive element on the top surface of the interconnect structure, wherein the second conductive element is electrically isolated from the interconnect structure;
a planarization stop layer conformally covering the first conductive element, the second conductive element, and the top surface of the interconnect structure;
a first dielectric material over the planarization stop layer and between the first conductive element and the second conductive element;
an etch stop layer over the planarization stop layer and the first dielectric material;
a second dielectric layer over the etch stop layer;
a first conductive feature extending through the second dielectric layer to physically contact the first conductive element; and
a second conductive feature extending through the second dielectric layer to physically contact the second conductive element.

### Claim 17 (depends on 16)

The device of claim 16, wherein the first conductive feature also extends through the planarization stop layer and the etch stop layer.

### Claim 18 (depends on 16)

The device of claim 16, wherein a thickness of the planarization stop layer on the top surface of the interconnect structure is greater than a thickness of the planarization stop layer on a top surface of the first conductive element.

### Claim 19 (depends on 16)

The device of claim 16, wherein a thickness of the first conductive element is greater than a thickness of the second conductive element.

### Claim 20 (depends on 16)

The device of claim 16, wherein the second dielectric layer, the first conductive feature, and the second conductive feature have level top surfaces.