# US 12,119,317 B2 · Singulation of microelectronic components with direct bonding interfaces > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,119,317 B2 - Document ID: US12119317B2 - Status: Granted - Kind: B2 - Application number: 17/032,469 - Filed: 2020-09-25 - Published: 2022-03-31 - Granted: 2024-10-15 - Earliest claimed: 2020-09-25 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Bhaskar Jyoti Krishnatreya; Nagatoshi Tsunoda; Shawna M. Liff; Sairam Agraharam - Web page: https://patentgrep.com/patent/US12119317B2 ## CPC - H10W 70/685: comprising multiple insulating layers - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/611: {for connecting multiple chips together} - H10W 70/65: Shapes or dispositions of interconnections - H10W 74/016: {using moulds} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 90/00: Package configurations - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 70/63: Vias, e.g. via plugs - H10W 72/0198: {batch processes} - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/926: {Multiple bond pads having different sizes} - H10W 72/931: {Shapes of bond pads} - H10W 72/936: {Multiple bond pads having different shapes} - H10W 72/944: {Dispositions of multiple bond pads} - H10W 72/951: {Materials of bond pads} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids} - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 80/312: {characterised by the direct bonding of electrically conductive pads} - H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers} - H10W 80/743: {having disposition changed during the connecting} - H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips} - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/792: {between multiple chips} - H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Disclosed herein are structures and techniques related to singulation of microelectronic components with direct bonding interfaces. For example, in some embodiments, a microelectronic component may include: a surface, wherein conductive contacts are at the surface; a trench at a perimeter of the surface; and a burr in the trench. ## Claims ### Claim 1 A microelectronic assembly, comprising: a first microelectronic component having a face having a first direct bonding interface, wherein the first microelectronic component has a trench at a perimeter of the face and having a depth; a burr in the trench having a height that is less than the depth of the trench; and a second microelectronic component having a second direct bonding interface, wherein the first direct bonding interface is direct bonded to the second direct bonding interface. ### Claim 2 (depends on 1) The microelectronic assembly of claim 1, wherein the first direct bonding interface includes conductive contacts. ### Claim 3 (depends on 2) The microelectronic assembly of claim 2, wherein a pitch of the conductive contacts is less than 20 microns. ### Claim 4 (depends on 2) The microelectronic assembly of claim 2, wherein the conductive contacts include copper. ### Claim 5 (depends on 2) The microelectronic assembly of claim 2, wherein the first direct bonding interface includes a dielectric material between adjacent ones of the conductive contacts. ### Claim 6 (depends on 5) The microelectronic assembly of claim 5, wherein the dielectric material includes an inorganic dielectric material. ### Claim 7 (depends on 1) The microelectronic assembly of claim 1, wherein the face is a first face, the trench is a first trench, the second direct bonding interface is at a second face of the second microelectronic component, and the second microelectronic component has a second trench at a perimeter of the second face. ### Claim 8 (depends on 7) The microelectronic assembly of claim 7, wherein the second microelectronic component includes a burr in the second trench. ### Claim 9 A system, comprising: a circuit board; and a microelectronic assembly, communicatively coupled to the circuit board, wherein the microelectronic assembly includes a face of a first microelectronic component direct bonded to a face of a second microelectronic component, and the face of the first microelectronic component includes a trench at its edges, wherein the trench has a depth and comprises a burr having a height that is less than the depth of the trench. ### Claim 10 (depends on 9) The system of claim 9, wherein the system further includes a display communicatively coupled to the circuit board. ### Claim 11 (depends on 1) The microelectronic assembly of claim 1, wherein the trench extends into a metallization stack of the first microelectronic component. ### Claim 12 (depends on 1) The microelectronic assembly of claim 1, wherein the trench extends into a substrate of the first microelectronic component. ### Claim 13 (depends on 12) The microelectronic assembly of claim 12, wherein the substrate includes a semiconductor material. ### Claim 14 (depends on 1) The microelectronic assembly of claim 1, wherein the burr is at an edge of the trench. ### Claim 15 (depends on 1) The microelectronic assembly of claim 1, wherein the burr has a height greater than 300 nanometers. ### Claim 16 (depends on 1) The microelectronic assembly of claim 1, wherein the burr includes material of a substrate of the first microelectronic component. ### Claim 17 (depends on 1) The microelectronic assembly of claim 1, wherein the first microelectronic component includes a substrate, and side surfaces of the substrate are convex, concave, or angled. ### Claim 18 (depends on 1) The microelectronic assembly of claim 1, wherein the first microelectronic component includes a substrate, and side surfaces of the substrate are jagged. ### Claim 19 (depends on 1) The microelectronic assembly of claim 1, wherein corners of the first microelectronic component are rounded.