# US 12,119,315 B2 · Chip bonding method and semiconductor chip structure

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- Number: US 12,119,315 B2
- Document ID: US12119315B2
- Status: Granted
- Kind: B2
- Application number: 17/650,851
- Filed: 2022-02-13
- Published: 2023-01-12
- Granted: 2024-10-15
- Earliest claimed: 2021-07-09
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Chih-Wei Chang
- Web page: https://patentgrep.com/patent/US12119315B2

## CPC

- H10W 90/00: Package configurations
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/071: {Connecting or disconnecting}
- H10W 72/073: {of die-attach connectors}
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 72/01951: {Changing the shapes of bond pads}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/9226: {with via interconnections}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/721: {having structure or size changed during the connecting}
- H10W 80/732: {having shape changed during the connecting}
- H10W 90/20: Configurations of stacked chips
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A chip bonding method includes the following operations. A first chip is provided, which includes a first contact pad including a first portion lower than a first surface of a first substrate and a second portion higher than the first surface of the first substrate to form the stepped first contact pad. A second chip is provided, which includes a second contact pad including a third portion lower than a third surface of a second substrate and a fourth portion higher than the third surface of the second substrate to form the stepped second contact pad. The first chip and the second chip are bonded. The first portion of the first chip contacts with the fourth portion of the second chip, and the second portion of the first chip contacts with the third portion of the second chip.

## Claims

### Claim 1

A chip bonding method, comprising:
providing a first chip, wherein the first chip comprises a first substrate comprising a first surface and a second surface which are arranged to be opposite, and the first chip further comprises a first groove on a side of the first surface of the first substrate and a first contact pad in the first groove, the first contact pad comprises a first portion and a second portion, the first portion is lower than the first surface of the first substrate and the second portion is higher than the first surface of the first substrate, so as to form the first contact pad which is stepped;
providing a second chip, wherein the second chip comprises a second substrate comprising a third surface and a fourth surface which are arranged to be opposite, and the second chip further comprises a second groove on a side of the third surface of the second substrate and a second contact pad in the second groove, the second contact pad comprises a third portion and a fourth portion, the third portion is lower than the third surface of the second substrate and the fourth portion is higher than the third surface of the second substrate, so as to form the second contact pad which is stepped;
bonding the first chip and the second chip, wherein the first portion of the first chip contacts with the fourth portion of the second chip, and the second portion of the first chip contacts with the third portion of the second chip; and
forming a gap between the first contact pad and the second contact pad after bonding the first chip and the second chip;
wherein the first chip further comprises a first through hole structure, the first through hole structure is disposed in the first substrate, and is on a side of the second surface of the first substrate, and a projection image of the gap falls within a projection image of the first through hole structure in a projection perpendicular to a plane direction of the first substrate; wherein the first groove is disposed above the first through hole structure; and
wherein the second chip further comprises a second through hole structure, the second through hole structure is disposed in the second substrate, and is on a side of the fourth surface of the second substrate, and a projection image of the gap falls within a projection image of the second through hole structure in a projection perpendicular to a plane direction of the second substrate; wherein the second groove is disposed above the second through hole structure.

### Claim 2 (depends on 1)

The method of claim 1, wherein
a side of a part of the second portion of the first contact pad is arc-shaped, and the part is higher than the first surface of the first substrate, and the side is close to the first substrate; and
a side of a part of the fourth portion of the second contact pad is arc-shaped, and the part is higher than the third surface of the second substrate, and the side is close to the second substrate.

### Claim 3 (depends on 1)

The method of claim 1, wherein
the projection image of the first through hole structure falls within a projection image of the first contact pad in the projection perpendicular to the plane direction of the first substrate; and
the projection image of the second through hole structure falls within a projection image of the second contact pad in the projection perpendicular to the plane direction of the second substrate.

### Claim 4 (depends on 1)

The method of claim 1, wherein
the first contact pad is circular or rectangular in a projection perpendicular to a plane direction of the first substrate; and
the second contact pad is circular or rectangular in a projection perpendicular to a plane direction of the second substrate.

### Claim 5 (depends on 1)

The method of claim 1, wherein
a width of the first portion is larger than half of a width of the first contact pad and a width of the third portion is larger than half of a width of the second contact pad, in an extending direction of steps.

### Claim 6 (depends on 5)

The method of claim 5, wherein
a height of a part of the second portion higher than the first portion ranges from 100 nm to 500 nm; and
a height of a part of the fourth portion higher than the third portion ranges from 100 nm to 500 nm.

### Claim 7 (depends on 1)

The method of claim 1, wherein
the providing the first chip comprises:
forming the first substrate comprising a first base plate, a first through hole structure penetrating through the first base plate and a first dielectric layer covering upper surfaces of the first base plate and the first through hole structure;
etching the first substrate to form the first groove disposed above the first through hole structure;
filling the first groove to form a first contact pad pre-layer; and
etching a part of the first contact pad pre-layer to form the first contact pad; and
the providing the second chip comprises:
forming the second substrate comprising a second base plate, a second through hole structure penetrating through the second base plate and a second dielectric layer covering upper surfaces of the second base plate and the second through hole structure;
etching the second substrate to form the second groove disposed above the second through hole structure;
filling the second groove to form a second contact pad pre-layer; and
etching a part of the second contact pad pre-layer to form the second contact pad.

### Claim 8 (depends on 1)

The method of claim 1, wherein
the bonding the first chip and the second chip comprises: bonding the first chip and the second chip up and down in a mirroring manner.

### Claim 9 (depends on 1)

The method of claim 1, wherein
the forming the gap between the first contact pad and the second contact pad comprises: forming a gap between the second portion of the first contact pad and the fourth portion of the second contact pad.

### Claim 10

A semiconductor chip structure, comprising:
a first chip comprising a first substrate comprising a first surface and a second surface which are arranged to be opposite, and the first chip further comprises a first groove on a side of the first surface of the first substrate and a first contact pad in the first groove;
a second chip comprising a second substrate comprising a third surface and a fourth surface which are arranged to be opposite, and the second chip further comprises a second groove on a side of the third surface of the second substrate and a second contact pad in the second groove; and
the first contact pad of the first chip contacts with the second contact pad of the second chip, and a gap is formed between the first contact pad and the second contact pad;
wherein the first chip further comprises a first through hole structure, the first through hole structure is disposed in the first substrate, and is on a side of the second surface of the first substrate, and a projection image of the gap falls within a projection image of the first through hole structure in a projection perpendicular to a plane direction of the first substrate; wherein the first groove is disposed above the first through hole structure; and
wherein the second chip further comprises a second through hole structure, the second through hole structure is disposed in the second substrate, and is on a side of the fourth surface of the second substrate, and a projection image of the gap falls within a projection image of the second through hole structure in a projection perpendicular to a plane direction of the second substrate; wherein the second groove is disposed above the second through hole structure.

### Claim 11 (depends on 10)

The semiconductor chip structure of claim 10, wherein
a side of a part of the first contact pad is arc-shaped, and the part protrudes from the first surface of the first substrate, and the side is close to the first substrate; and
a side of a part of the second contact pad is arc-shaped, and the part protrudes from the third surface of the second substrate, and the side is close to the second substrate.

### Claim 12 (depends on 10)

The semiconductor chip structure of claim 10, wherein
the projection image of the first through hole structure falls within a projection image of the first contact pad in the projection perpendicular to the plane direction of the first substrate; and
the projection image of the second through hole structure falls within a projection image of the second contact pad in the projection perpendicular to the plane direction of the second substrate.

### Claim 13 (depends on 10)

The semiconductor chip structure of claim 10, wherein
the first contact pad is circular or rectangular in a projection perpendicular to a plane direction of the first substrate; and
the second contact pad is circular or rectangular in a projection perpendicular to a plane direction of the second substrate.

### Claim 14 (depends on 10)

The semiconductor chip structure of claim 10, wherein
the first contact pad comprises a first portion and a second portion, the first portion is lower than the first surface of the first substrate and the second portion is higher than the first surface of the first substrate, so as to form the first contact pad which is stepped; and
the second contact pad comprises a third portion and a fourth portion, the third portion is lower than the third surface of the second substrate and the fourth portion is higher than the third surface of the second substrate, so as to form the second contact pad which is stepped.
