# US 12,119,308 B2 · Packaging structure of semiconductor chip and formation method thereof

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,119,308 B2
- Document ID: US12119308B2
- Status: Granted
- Kind: B2
- Application number: 17/629,549
- Filed: 2020-07-17
- Published: 2022-08-25
- Granted: 2024-10-15
- Earliest claimed: 2019-07-26
- Assignees: Tongfu Microelectronics Co., Ltd.
- Applicants: Tongfu Microelectronics Co., Ltd.
- Inventors: Xiaoyong Miao; Honghui Wang
- Web page: https://patentgrep.com/patent/US12119308B2

## CPC

- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 70/685: comprising multiple insulating layers
- H10W 72/0198: {batch processes}
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/014: {using batch processing}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01238: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01951: {Changing the shapes of bond pads}
- H10W 72/01955: {by using masks}
- H10W 72/072: {of bump connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/354: {comprising polymers}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A packaging structure and fabrication method thereof are provided. The method includes: providing semiconductor chips including soldering pads and metal bumps; providing a base plate, wiring structures, input terminals, and output terminals; mounting the semiconductor chips on the front surface of the base plate inversely, such that each metal bump is connected to a corresponding input terminal; forming a bottom filling layer between a functional surface of each semiconductor chip and the front surface of the base plate; forming a first shielding layer covering a non-functional surface and sidewalls of each semiconductor chip, and covering sidewalls of a corresponding bottom filling layer; forming a second shielding layer on each first shielding layer; forming a plastic encapsulation layer on second shielding layers and on a portion of the base plate between semiconductor chips; and forming external contact structures connected to the output terminals.

## Claims

### Claim 1

A fabrication method for a packaging structure, comprising:
providing semiconductor chips, wherein each semiconductor chip includes a functional surface and a non-functional surface opposite to the functional surface;
providing soldering pads on functional surfaces of the semiconductor chips, and a metal bump on each soldering pad;
providing a base plate, wiring structures in the base plate, input terminals on a front surface of the base plate, and output terminals on a back surface of the base plate, wherein the input terminals and the output terminals are connected to corresponding wiring structures respectively;
mounting the semiconductor chips on the front surface of the base plate inversely, wherein each metal bump on the semiconductor chips is connected to a corresponding input terminal on the front surface of the base plate;
forming a bottom filling layer between the functional surface of each semiconductor chip and the front surface of the base plate;
forming a bottom shielding layer and an isolation layer, interlaced along a lateral direction of the base plate over the bottom filling layer, wherein each soldering pad penetrates through the interlaced isolation layer;
forming a first shielding layer covering the non-functional surface and sidewalls of each semiconductor chip, and covering sidewalls of a corresponding bottom filling layer, and further being in contact with edges of the bottom shielding layer;
forming a second shielding layer on each first shielding layer;
forming a plastic encapsulation layer on second shielding layers and on a portion of the base plate between semiconductor chips; and
forming external contact structures on the back surface of the base plate and connected to the output terminals.

### Claim 2 (depends on 1)

The method according to claim 1, wherein:
the first shielding layer is formed by a sputtering process and further covers at least a portion of the base plate at sides of a corresponding semiconductor chip; and
after forming the second shielding layer, a portion of the first shielding layer on the portion of the base plate at the sides of the corresponding semiconductor chip is removed.

### Claim 3 (depends on 2)

The method according to claim 2, wherein:
the second shielding layer is disposed only on a portion of the first shielding layer on the non-functional surfaces and the sidewalls of the corresponding semiconductor chip;
the second shielding layer has an ellipsoidal surface; and
the second shielding layer is formed by a selective plating process, a dispersing process, or a mesh printing process.

### Claim 4 (depends on 3)

The method according to claim 3, wherein:
the first shielding layer is made of copper, tungsten, aluminum, or a combination thereof; and
the second shielding layer is made of copper, solder, conductive silver paste, or a combination thereof.

### Claim 5 (depends on 1)

The method according to claim 1, wherein:
the first shielding layer is a magnetic field shielding layer and the second shielding layer is an electric field shielding layer; or
the first shielding layer is an electric field shielding layer and the second shielding layer is a magnetic field shielding layer.

### Claim 6 (depends on 5)

The method according to claim 5, wherein:
the electric field shielding layer is made of copper, tungsten, aluminum, or a combination thereof; and
the magnetic field shielding layer is made of CoFeB, CoFeTa, NiFe, Co, CoFe, CoPt, Ni—Co—Fe alloy, or a combination thereof.

### Claim 7 (depends on 1)

The method according to claim 1, wherein:
surrounding edges of the bottom shielding layer are flush with surrounding sidewalls of the corresponding semiconductor chip.

### Claim 8 (depends on 7)

The method according to claim 7, wherein the semiconductor chips with the bottom shielding layers are formed by:
providing a wafer;
forming the semiconductor chips on the wafer, wherein each semiconductor chip includes a top dielectric layer and a top interconnection structure in the top dielectric layer;
forming an isolation layer on the top dielectric layer of each semiconductor chip;
etching isolation layers to form first openings and second openings surrounding the first openings, wherein a remaining portion of the isolation layers are only located between the first openings and the second openings to separate the first openings from the second openings;
filling the first openings with metal to form the soldering pads;
filling the second openings with metal to form the bottom shielding layers;
forming a metal bump on each soldering pad; and
cutting the wafer to form the discrete semiconductor chips with the bottom shielding layers.

### Claim 9 (depends on 8)

The method according to claim 8, wherein:
the soldering pads and the bottom shielding layers are formed by a same process including: forming a metal material layer in the first openings and the second openings, and on surfaces of the isolation layers; and planarizing the metal material layer to remove a portion of the metal material layer higher than the surfaces of the isolation layers, to form the soldering pads in the first openings and the bottom shielding layers in the second openings.

### Claim 10 (depends on 1)

The method according to claim 1 wherein:
each external contact structure includes a soldering ball, or a metal post and a soldering ball on the metal post.

### Claim 11 (depends on 1)

The method according to claim 1, further including:
forming conductive contact structures in the base plate, wherein the conductive contact structures are electrically connected to the first shielding layers.

### Claim 12 (depends on 1)

The method according to claim 1, further including:
after forming the external contact structures, cutting the pre-packaging plate to form discrete packaging structures.

### Claim 13 (depends on 1)

The method according to claim 1, wherein:
the first shielding layer has an ellipsoidal surface;
the first shielding layer is formed directly on the non-functional surface and the sidewalls of the corresponding semiconductor chip by a dispersing process or a mesh printing process; and
the second shielding layer is formed by a sputtering process, a selective plating process, a dispersing process, or a mesh printing process.

### Claim 14 (depends on 13)

The method according to claim 13, wherein:
the first shielding layer is made of solder, conductive silver paste, or a combination thereof; and
the second shielding layer is made of copper, tungsten, aluminum, solder, conductive silver paste, or a combination thereof.

### Claim 15 (depends on 13)

The method according to claim 13, before forming the first shielding layer, further including forming an intermediate material layer on the non-functional surface and the sidewalls of each semiconductor chip, wherein:
the intermediate material layer has an ellipsoidal surface;
the first shielding layer is formed on a corresponding intermediate material layer; and
the first shielding layer has the ellipsoidal surface.

### Claim 16

A packaging structure, comprising:
a base plate, wiring structures in the base plate, input terminals on a front surface of the base plate, and output terminals on a back surface of the base plate, wherein the input terminals and the output terminals are connected to corresponding wiring structures respectively;
semiconductor chips mounted on the front surface of the base plate inversely, wherein each semiconductor chip includes a functional surface, and a non-functional surface opposite to the functional surface, soldering pads on the functional surface, and a metal bump on each soldering pad, wherein each metal bump is connected to a corresponding input terminal on the front surface of the base plate;
a bottom filling layer between a functional surface of each semiconductor chip and the front surface of the base plate;
a first shielding layer surrounding the non-functional surface and sidewalls of each semiconductor chip and a corresponding bottom filling layer;
a second shielding layer on each first shielding layer;
a bottom shielding layer and an isolation layer, interlaced along a lateral direction of the base plate between the functional surface of each semiconductor chip and the bottom filling layer, wherein
the bottom shielding layer includes edges being in contact with a sidewall of the first shielding layer, and
each soldering pad penetrates through the interlaced isolation layer; and
external contact structures connected to the output terminals and on the back surface of the base plate.

### Claim 17 (depends on 16)

The packaging structure according to claim 16, wherein:
the first shielding layer is formed by a sputtering process and further covers at least a portion of the base plate at sides of a corresponding semiconductor chip; and
the second shielding layer is formed by a selective plating process, a dispersing process, or a mesh printing process.

### Claim 18 (depends on 16)

The packaging structure according to claim 16, wherein:
the first shielding layer has an ellipsoidal surface.

### Claim 19 (depends on 18)

The packaging structure according to claim 18, further including an intermediate material layer on the non-functional surface and the sidewalls of each semiconductor chip, wherein:
the intermediate material layer has an ellipsoidal surface;
the first shielding layer is formed on a corresponding intermediate material layer; and
the first shielding layer has the ellipsoidal surface.

### Claim 20

A discrete packaging structure formed by cutting a package structure, comprising:
a base plate, wiring structures in the base plate, input terminals on a front surface of the base plate, and output terminals on a back surface of the base plate, wherein the input terminals and the output terminals are connected to corresponding wiring structures respectively;
a semiconductor chip mounted on the front surface of the base plate inversely, wherein the semiconductor chip includes a functional surface, a non-functional surface opposite to the functional surface, soldering pads on the functional surface, and a metal bump on each soldering pad, wherein each metal bump is connected to a corresponding input terminal on the front surface of the base plate;
a bottom filling layer between the functional surface of the semiconductor chip and the front surface of the base plate;
a first shielding layer surrounding the non-functional surface and sidewalls of the semiconductor chip and a corresponding bottom filling layer;
a second shielding layer on the first shielding layer;
a bottom shielding layer and an isolation layer, interlaced along a lateral direction of the base plate between the functional surface of each semiconductor chip and the bottom filling layer, wherein
the bottom shielding layer includes edges being in contact with a sidewall of the first shielding layer, and
each soldering pad penetrates through the interlaced isolation layer; and
external contact structures connected to the output terminals and on the back surface of the base plate.