# US 12,119,307 B2 · Integrated self-aligned assembly > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,119,307 B2 - Document ID: US12119307B2 - Status: Granted - Kind: B2 - Application number: 17/504,125 - Filed: 2021-10-18 - Published: 2022-04-21 - Granted: 2024-10-15 - Earliest claimed: 2020-10-19 - Assignees: Rockley Photonics Limited - Applicants: Rockley Photonics Limited - Inventors: Chia-Te Chou; Brett Sawyer; David McCann - Web page: https://patentgrep.com/patent/US12119307B2 ## CPC - H10W 46/00: Marks applied to devices, e.g. for alignment or identification - H10W 46/301: {for alignment} - H10W 46/607: {Located on parts of packages, e.g. on encapsulations or on package substrates} - H10W 70/611: {for connecting multiple chips together} - H10W 70/63: Vias, e.g. via plugs - H10W 70/68: Shapes or dispositions thereof - H10W 70/685: comprising multiple insulating layers - H10W 72/231: {Shapes} - H10W 72/263: {Providing mechanical bonding or support, e.g. dummy bumps} - H10W 72/267: {Multiple bump connectors having different functions} - H10W 90/00: Package configurations - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/725: {between a chip and a laterally-adjacent insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An assembly. In some embodiments, the assembly includes a first semiconductor chip, a substrate, and a first alignment element. The alignment of the first semiconductor chip and the substrate may be determined at least in part by engagement of the first alignment element with a first recessed alignment feature, in a surface of the first semiconductor chip. ## Claims ### Claim 1 An assembly, comprising: a first semiconductor chip; a substrate; and a first alignment element, wherein the alignment of the first semiconductor chip and the substrate is determined at least in part by engagement of the first alignment element with a first recessed alignment feature, in a surface of the first semiconductor chip and extending part way through the first semiconductor chip, and wherein the first alignment element is a pin elongated along an axis, a first end of the pin being secured in a hole in the substrate, and the axis extending from the substrate to the first semiconductor chip. ### Claim 2 (depends on 1) The assembly of claim 1, wherein the first recessed alignment feature has a face aligned with a crystalline plane of the first semiconductor chip. ### Claim 3 (depends on 2) The assembly of claim 2, wherein the first recessed alignment feature has the shape of a pyramid or of a truncated pyramid. ### Claim 4 (depends on 2) The assembly of claim 2, wherein the first recessed alignment feature has the shape of a V-groove or of a truncated V-groove. ### Claim 5 (depends on 1) The assembly of claim 1, wherein the elongated pin is a cylindrical pin. ### Claim 6 (depends on 5) The assembly of claim 5, wherein a second end of the cylindrical pin is hemispherical and engages the first recessed alignment feature. ### Claim 7 (depends on 6) The assembly of claim 6, wherein the first semiconductor chip is a photonic integrated circuit having an optical interface and an electrical interface, the photonic integrated circuit being configured to convert optical signals to electrical signals or to convert electrical signals to optical signals. ### Claim 8 (depends on 7) The assembly of claim 7, further comprising an interface integrated circuit connected to the electrical interface of the photonic integrated circuit, and connected, through a land grid array and through a socket, to the substrate. ### Claim 9 (depends on 7) The assembly of claim 7, wherein the first recessed alignment feature has the shape of a pyramid or of a truncated pyramid. ### Claim 10 (depends on 7) The assembly of claim 7, wherein the first recessed alignment feature has the shape of a V-groove or of a truncated V-groove. ### Claim 11 (depends on 6) The assembly of claim 6, further comprising a photonic integrated circuit, wherein: the photonic integrated circuit has an optical interface and an electrical interface, and is configured to convert optical signals to electrical signals or to convert electrical signals to optical signals. ### Claim 12 (depends on 11) The assembly of claim 11, comprising an interface integrated circuit connected to the electrical interface of the photonic integrated circuit, and connected, through land grid array and through a socket, to the substrate. ### Claim 13 (depends on 12) The assembly of claim 12, wherein the first alignment element extends through the socket. ### Claim 14 (depends on 12) The assembly of claim 12, wherein: the first semiconductor chip is a carrier; and the interface integrated circuit and the photonic integrated circuit are secured to the carrier. ### Claim 15 (depends on 14) The assembly of claim 14, wherein the photonic integrated circuit has an active surface facing the carrier, and a second alignment element engages: a second recessed alignment feature, in the photonic integrated circuit, and a third recessed alignment feature, in the carrier. ### Claim 16 (depends on 15) The assembly of claim 15, wherein the first recessed alignment feature has the shape of a pyramid or of a truncated pyramid. ### Claim 17 (depends on 15) The assembly of claim 15, wherein the first recessed alignment feature has the shape of a V-groove or of a truncated V-groove. ### Claim 18 (depends on 15) The assembly of claim 15, wherein the second recessed alignment feature has the shape of a pyramid or of a truncated pyramid. ### Claim 19 (depends on 15) The assembly of claim 15, wherein the second recessed alignment feature has the shape of a V-groove or of a truncated V-groove. ### Claim 20 (depends on 15) The assembly of claim 15, wherein an angle between a sloped surface of the second recessed alignment feature and the active surface is between 50 degrees and 60 degrees. ### Claim 21 An assembly, comprising: a first semiconductor chip; a substrate; and a first alignment element, wherein the alignment of the first semiconductor chip and the substrate is determined at least in part by engagement of the first alignment element with a first recessed alignment feature, in a surface of the first semiconductor chip and extending part way through the first semiconductor chip, wherein the first alignment element is a cylindrical pin extending along an axis and having: a first end at one end of the axis and that is secured in a hole in the substrate; and a second end at another end of the axis and that is round and engages the first recessed alignment feature. ### Claim 22 An assembly, comprising: a first semiconductor chip; a substrate; and a first alignment element, wherein the alignment of the first semiconductor chip and the substrate is determined at least in part by engagement of the first alignment element with a first recessed alignment feature, in a surface of the first semiconductor chip, wherein the first alignment element is an elongated pin having a first end secured in a hole in the substrate, wherein: the first semiconductor chip is a photonic integrated circuit having an optical interface and an electrical interface, the photonic integrated circuit being configured to convert optical signals to electrical signals or to convert electrical signals to optical signals; or the assembly further comprises a photonic integrated circuit having an optical interface and an electrical interface, and being configured to convert optical signals to electrical signals or to convert electrical signals to optical signals, and wherein the assembly further comprises an interface integrated circuit connected to the electrical interface of the photonic integrated circuit, and connected, through a land grid array and through a socket, to the substrate.