# US 12,119,304 B2 · Very fine pitch and wiring density organic side by side chiplet integration

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- Number: US 12,119,304 B2
- Document ID: US12119304B2
- Status: Granted
- Kind: B2
- Application number: 17/321,080
- Filed: 2021-05-14
- Published: 2022-03-31
- Granted: 2024-10-15
- Earliest claimed: 2020-09-25
- Assignees: Apple Inc.
- Applicants: Apple Inc.
- Inventors: Sanjay Dabral; Zhitao Cao; Kunzhong Hu
- Web page: https://patentgrep.com/patent/US12119304B2

## CPC

- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects}
- H10W 20/4421: {the principal metal being copper}
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 74/01: Manufacture or treatment
- H10W 74/014: {using batch processing}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/10: characterised by their shape or disposition
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 74/141: {the encapsulations being on at least the sidewalls of the semiconductor body}
- H10W 90/00: Package configurations
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/685: comprising multiple insulating layers
- H10W 70/695: Organic materials
- H10W 72/0198: {batch processes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/9413: {on encapsulations}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Structures and methods of forming fine die-to-die interconnect routing are described. In an embodiment, a package includes a package-level RDL than spans across a die set and includes a plurality of die-to-die interconnects connecting contact pads between each die. In an embodiment, the plurality of die-to-die interconnects is embedded within one or more photoimageable organic dielectric layers.

## Claims

### Claim 1

A package comprising:
a die set encapsulated in a molding compound layer;
a package-level redistribution layer (RDL) spanning across the die set and the molding compound layer and on and in electrical connection with the die set;
wherein each die in the die set includes a die-level back end of the line (BEOL) build-up structure including a plurality of contact pads, a passivation layer, and a plurality of openings in the passivation layer exposing the plurality of contact pads; and
wherein the package-level RDL includes a plurality of die-to-die interconnects connecting the plurality of contact pads between each die and embedded within a plurality of vias and trenches formed in a plurality of photoimageable organic dielectric layers, the plurality of vias including a group of vias formed directly on the plurality of contact pads for each die in the die set, wherein each via has a perimeter that is smaller than a corresponding opening in the passivation layer that exposes a corresponding contact pad which the via is directly formed on.

### Claim 2 (depends on 1)

The package of claim 1, wherein the plurality of die-to-die interconnects comprise damascene interconnects, and the BEOL build-up structure for each die in the die set includes damascene metal wiring layers.

### Claim 3 (depends on 2)

The package of claim 2, wherein the damascene interconnects comprise copper damascene interconnects.

### Claim 4 (depends on 2)

The package of claim 2, wherein the damascene interconnects include multi-layer damascene interconnects including damascene interconnect lines within multiple metal layers in the package-level RDL.

### Claim 5 (depends on 2)

The package of claim 2, wherein the group of vias formed directly on the plurality of contact pads for each die in the die set are a same height.

### Claim 6 (depends on 2)

The package of claim 2, wherein the damascene interconnects include a first die-to-die interconnect that includes a first damascene via directly on a first contact pad of a first die, a second damascene via directly on a second contact pad of a second die, and a damascene interconnect line connecting the first damascene via and the second damascene via, wherein the first damascene via, the second damascene via and the damascene interconnect line are a continuous metal layer.

### Claim 7 (depends on 2)

The package of claim 2, wherein perimeters of the group plurality of vias are separated from perimeters of the plurality of contacts pads by a mean minimum offset distance of less than 3 microns.

### Claim 8 (depends on 2)

The package of claim 2, wherein:
the die set includes a first die and a second die; and
the package-level RDL includes first intra-die interconnections for the first die and second intra-die interconnections for the second die.

### Claim 9 (depends on 2)

The package of claim 2, wherein the BEOL build-up structure for each die includes plurality of test contact pads, wherein the package-level RDL is not electrically connected to the test contact pads for each die.

### Claim 10 (depends on 9)

The package of claim 9, wherein the plurality of contact pads is a plurality of aluminum pads.

### Claim 11 (depends on 1)

The package of claim 1, wherein:
the package-level RDL includes a plurality of vias formed directly on the plurality of contact pads for each die in the die set; and
perimeters of the plurality of vias are separated from perimeters of the plurality of contacts pads by a mean minimum offset distance of less than 3 microns.

### Claim 12 (depends on 11)

The package of claim 11, wherein:
the die set includes a first die and a second die;
the plurality of vias includes a first via directly on a first contact pad of the first die, and a second via directly on a second contact pad of the second die; and
a dual damascene die-to-die interconnect that includes a first damascene via directly on the first via, second damascene via directly on the second via, and a damascene interconnect line connecting the first damascene via and the second damascene via, wherein the first damascene via, the second damascene via and the damascene interconnect line are a continuous metal layer.

### Claim 13 (depends on 1)

The package of claim 1:
further comprising an inorganic barrier layer over the die set, and between the die set and the molding compound layer; and
wherein the package-level RDL spans over the inorganic barrier layer laterally between dies in the die set.

### Claim 14 (depends on 13)

The package of claim 13, wherein the plurality of die-to-die interconnects comprise a first dual damascene die-to-die interconnect that includes:
a first damascene via connected to a first contact pad of a first die, a second damascene via connected to a second contact pad of a second die, and a damascene interconnect line connecting the first damascene via and the second damascene via, wherein the first damascene via, the second damascene via and the damascene interconnect line are a continuous metal layer, and wherein the damascene interconnect line spans directly over the inorganic barrier layer laterally between the first die and the second die.

### Claim 15 (depends on 1)

The package of claim 1, wherein the plurality of contact pads for each die are separated by a pad pitch of less than 5 μm.

### Claim 16 (depends on 15)

The package of claim 15, wherein the plurality of die-to-die interconnects includes side-by-side interconnect lines with a line width of less than 1 μm and spacing between of less than 1 μm.

### Claim 17

A package comprising:
a die set encapsulated in a molding compound layer;
an inorganic barrier layer over the die set, and between the die set and the molding compound layer;
a package-level redistribution layer (RDL) spanning across the molding compound layer and on and in electrical connection with the die set;
wherein the package-level RDL spans across the inorganic barrier layer laterally between dies in the die set;
wherein each die in the die set includes a die-level back end of the line (BEOL) build-up structure including a plurality of contact pads; and
wherein the package-level RDL includes a plurality of die-to-die interconnects connecting the plurality of contact pads between each die.

### Claim 18 (depends on 17)

The package of claim 17, wherein the package-level RDL includes an organic dielectric layer spanning across the die set, and a plurality of vias extending through the organic dielectric layer and directly on a plurality of contact pads for each die in the die set.

### Claim 19 (depends on 18)

The package of claim 18, wherein perimeters of the plurality of vias are separated from perimeters of the plurality of contacts pads by a mean minimum offset distance of less than 3 microns.

### Claim 20 (depends on 18)

The package of claim 18, wherein the plurality of vias are part of damascene interconnects.

### Claim 21 (depends on 20)

The package of claim 20, wherein the damascene interconnects in include damascene interconnect lines connecting the plurality of vias between plurality of contact pads for each die in the die set, and the damascene interconnect lines are directly over the inorganic barrier layer laterally between the die set.

### Claim 22

A method comprising:
placing a die set face down on a carrier substrate, each die in the die set includes a die-level back end of the line (BEOL) build-up structure including a plurality of contact pads, a passivation layer, and a plurality of openings in the passivation layer exposing the plurality of contact pads;
encapsulating the die set in a molding compound;
removing the carrier substrate;
measuring a location of the die set;
comparing the measured location of the die set to a baseline location, and determining a modified wiring pattern; and
forming a package-level redistribution layer (RDL) over the die set based on the modified wiring pattern to form a plurality of die-to-die interconnects in a plurality of photoimageable polymer layers by developing permanent areas of the plurality of photoimageable polymer layers followed by dissolving undeveloped areas of the photoimageable polymer layers;
wherein package-level RDL spans across the die set and the molding compound layer and is on and-in electrical connection with the die set, and the plurality of die-to-die interconnects connects the plurality of contact pads between each die and is embedded within a plurality of vias and trenches formed in the plurality of photoimageable organic dielectric layers, the plurality of vias including a group of vias formed directly on the plurality of contact pads for each die in the die set, wherein each via has a perimeter that is smaller than a corresponding opening in the passivation layer that exposes a corresponding contact pad which the via is directly formed on.

### Claim 23 (depends on 22)

The method of claim 22, further comprising depositing an inorganic barrier layer liner over the die set and the carrier substrate prior to encapsulating the die set in the molding compound.

### Claim 24 (depends on 23)

The method of claim 23, wherein the package-level RDL comprises forming dual damascene die-to-die interconnects.

### Claim 25

A chip comprising:
a die area set formed in a same semiconductor layer;
a back end of the line (BEOL) build-up structure formed over the die area set, the BEOL build-up structure including a plurality of contact pads;
a chip-level redistribution layer (RDL) spanning across the BEOL build-up structure and over the die area set;
wherein the chip-level RDL includes a plurality of die area-to-die area interconnects connecting the plurality of contact pads between each die area; and
wherein the BEOL build-up structure includes a plurality of lower metallic seals, each lower metallic seal around a corresponding die area, and the chip level-RDL includes an upper metallic seal that overlies outer perimeters of the plurality of lower metallic seals.

### Claim 26 (depends on 25)

The chip of claim 25, wherein the plurality of die area-to-die area interconnects is embedded within one or more photoimageable organic dielectric layers.

### Claim 27 (depends on 26)

The chip of claim 26, wherein the back end of the line (BEOL) build-up structure includes a plurality of wiring layers formed in inorganic dielectric layers.

### Claim 28 (depends on 25)

The chip of claim 25, wherein the plurality of die-to-die interconnects are formed before testing, and further comprising a side surface of the chip-level RDL including a plurality of cut interconnect lines.