# US 12,119,300 B2 · Transistor circuits with shielded reference transistors > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,119,300 B2 - Document ID: US12119300B2 - Status: Granted - Kind: B2 - Application number: 17/663,181 - Filed: 2022-05-12 - Published: 2023-11-16 - Granted: 2024-10-15 - Earliest claimed: 2022-05-12 - Assignees: NXP USA, Inc. - Applicants: NXP USA, Inc. - Inventors: Humayun Kabir; Ibrahim Khalil; Daniel Joseph Lamey; Yu-Ting David Wu - Web page: https://patentgrep.com/patent/US12119300B2 ## CPC - H03F 1/301: {in MOSFET amplifiers (H03F1/303, H03F1/305, H03F1/308 take precedence)} - H10W 20/43: Layouts of interconnections - H03F 1/0288: {using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers} - H03F 3/195: in integrated circuits - H03K 17/6871: {the output circuit comprising more than one controlled field-effect transistor} - H10D 64/01: Manufacture or treatment - H10D 64/251: {Source or drain electrodes for field-effect devices} - H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)} - H10D 64/519: {characterised by their top-view geometrical layouts} - H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/83: of only insulated-gate FETs [IGFET] - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 20/212: {Top-view shapes or dispositions, e.g. top-view layouts of the vias} - H10W 90/00: Package configurations - H10D 84/82: of only field-effect components - H10W 44/20: at high-frequency [HF] or radio frequency [RF] - H03F: AMPLIFIERS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A device having a reference transistor fabricated within the same semiconductor substrate as a primary transistor (e.g., configured for use in a radiofrequency amplifier or other active circuit) has a shared metallization area coupled to a current terminal of both transistors configured to shield a control terminal of the reference transistor from coupling of alternating current interference from alternating currents within the primary transistor. ## Claims ### Claim 1 A semiconductor device, comprising: a primary transistor formed within a semiconductor substrate, the primary transistor having a first current terminal, a second current terminal, and a control terminal; a reference transistor adjacent to the primary transistor formed within the semiconductor substrate, the reference transistor having a first current terminal, a second current terminal, and a control terminal; and a bias controller configured to operate the primary transistor at a desired operating point by: applying predetermined bias voltages to the current terminals and the control terminal of the reference transistor; measuring a reference electrical current level flowing between the first current terminal and the second current terminal of the reference transistor; and applying bias voltages configured to operate the primary transistor at the desired operating point that are derived from the reference current level to the primary transistor; wherein the device further comprises: a first gate metallization area of the semiconductor substrate that is electrically coupled to the control terminal of the primary transistor; a second gate metallization area of the semiconductor substrate that is electrically coupled to the control terminal of the reference transistor; and a shared metallization area of the semiconductor substrate that is coupled to both the first current terminal of the primary transistor and to the first current terminal of the reference transistor; wherein the shared metallization area includes a metallized extension that is disposed between the first gate metallization area and the second gate metallization area and the metallized extension is configured to shield the control terminal of the reference transistor from alternating-current signals applied to the current terminal of the primary transistor; and wherein the shared metallization area is configured such that the first current terminal of the reference transistor is electrically coupled to the first current terminal of the primary transistor through the shared metallization area. ### Claim 2 A semiconductor device, comprising: a primary transistor formed within a semiconductor substrate, the primary transistor having a first current terminal, a second current terminal, and a control terminal; a reference transistor adjacent to the primary transistor formed within the semiconductor substrate, the reference transistor having a first current terminal, a second current terminal, and a control terminal; a first gate metallization area of the semiconductor substrate that is electrically coupled to the control terminal of the primary transistor; a second gate metallization area of the semiconductor substrate that is electrically coupled to the control terminal of the reference transistor; and a shared metallization area of the semiconductor substrate that is coupled to both the first current terminal of the primary transistor and to the first current terminal of the reference transistor; wherein the shared metallization area includes a first metallized extension that is disposed between the first gate metallization area and the second gate metallization area and the first metallized extension is configured to shield the control terminal of the reference transistor from alternating-current signals applied to the current terminal of the primary transistor; and wherein the shared metallization area is configured such that the first current terminal of the reference transistor is electrically coupled to the first current terminal of the primary transistor through the shared metallization area. ### Claim 3 (depends on 2) The semiconductor device of claim 2, wherein the shared metallization area further includes a second metallized extension that is disposed between a first drain metallization area of the semiconductor substrate that is electrically coupled to the second current terminal of the primary transistor and a second drain metallization area of the semiconductor substrate electrically coupled to the second current terminal of the reference transistor. ### Claim 4 (depends on 2) The semiconductor device of claim 2, wherein the primary transistor is formed within a first portion of the semiconductor substrate and the reference transistor is formed within a second portion of the semiconductor substrate; and wherein the first portion of the semiconductor substrate and the second portion of the semiconductor substrate are disposed on opposite sides of the common metalized area. ### Claim 5 (depends on 2) The semiconductor device of claim 2, wherein the first gate metallization area is separated from the second gate metallization area by a first metallized extension of the shared metallization area that is spaced apart from both the first gate metallization area and the second gate metallization area. ### Claim 6 (depends on 5) The semiconductor device of claim 5, wherein the first metallized extension of the shared metallization area extends in a first direction and is disposed between the first gate metallization area and the second gate metallization area. ### Claim 7 (depends on 6) The semiconductor device of claim 6, wherein a second metallized extension of the shared metallization area extends in a second direction that is at least partially orthogonal to the first direction; wherein the second metallized extension of the shared metallization area is disposed between a first drain metallization area electrically coupled to the second current terminal of the primary transistor and a second drain metallization area electrically coupled to the second current terminal of the reference transistor; and wherein the second metallized extension of the shared metallization area is spaced apart from both the first drain metallization area and the second drain metallization area. ### Claim 8 (depends on 2) The semiconductor device of claim 2, wherein the shared metallization area is coupled to a reference voltage node of the semiconductor substrate by one or more electrically conductive vias within the semiconductor substrate. ### Claim 9 (depends on 2) The semiconductor device of claim 2, wherein an edge of the first gate metallization area closest to the second gate metallization area is separated from the second gate metallization area by a distance in an inclusive range between 10 μm and 50 μm. ### Claim 10 (depends on 2) The semiconductor device of claim 2, further comprising; a set of two or more electrically conductive source electrode fingers of the primary transistor that are coupled to the shared metallization area; a set of two or more electrically conductive drain electrode fingers of the primary transistor in an interdigitated arrangement with the source electrode fingers; and a set of two or more electrically conductive gate metallization area fingers of the primary transistor that are disposed in an interdigitated arrangement with the source electrode fingers and the drain electrode fingers. ### Claim 11 (depends on 2) The semiconductor device of claim 2, wherein the first gate metallization area, the second gate metallization area, and the shared metallization area are formed from a single layer of conductive material on the surface of the semiconductor substrate. ### Claim 12 A method of forming a semiconductor device, comprising: forming a primary transistor within a semiconductor substrate, the primary transistor having a first current terminal, a second current terminal, and a control terminal; forming a reference transistor adjacent to the primary transistor within the semiconductor substrate, the reference transistor having a first current terminal, a second current terminal, and a control terminal; forming a first gate metallization area of the semiconductor substrate that is electrically coupled to the control terminal of the primary transistor; forming a second gate metallization area of the semiconductor substrate that is electrically coupled to the control terminal of the reference transistor; and forming a shared metallization area of the semiconductor substrate that is coupled to both the first current terminal of the primary transistor and to the first current terminal of the reference transistor; wherein forming the shared metallization area includes forming a first metallized extension that is disposed between the first gate metallization area and the second gate metallization area; wherein the first metallized extension is configured to shield the control terminal of the reference transistor from alternating-current signals applied to the current terminal of the primary transistor; and wherein the shared metallization area is configured such that the first current terminal of the reference transistor is electrically coupled to the first current terminal of the primary transistor through the shared metallization area. ### Claim 13 (depends on 12) The method of claim 12, wherein the shared metallization area further includes a second metallized extension that is disposed between a first drain metallization area of the semiconductor substrate that is electrically coupled to the second current terminal of the primary transistor and a second drain metallization area of the semiconductor substrate electrically coupled to the second current terminal of the reference transistor. ### Claim 14 (depends on 12) The method of claim 12, wherein the primary transistor is formed within a first portion of the semiconductor substrate and the reference transistor is formed within a second portion of the semiconductor substrate; and wherein the first portion of the semiconductor substrate and the second portion of the semiconductor substrate are disposed on opposite sides of the common metalized area. ### Claim 15 (depends on 12) The method of claim 12, wherein the first gate metallization area is separated from the second gate metallization area by a first metallized extension of the shared metallization area that is spaced apart from both the first gate metallization area and the second gate metallization area. ### Claim 16 (depends on 15) The method of claim 15, wherein the first metallized extension of the shared metallization area extends in a first direction and is disposed between the first gate metallization area and the second gate metallization area. ### Claim 17 (depends on 16) The method of claim 16, further comprising: forming a second metallized extension of the shared metallization area extends in a second direction that is at least partially orthogonal to the first direction; wherein the second metallized extension of the shared metallization area is disposed between a first drain metallization area electrically coupled to the second current terminal of the primary transistor and a second drain metallization area electrically coupled to the second current terminal of the reference transistor; and wherein the second metallized extension of the shared metallization area is spaced apart from both the first drain metallization area and the second drain metallization area. ### Claim 18 (depends on 12) The method of claim 12, further comprising; forming a set of two or more electrically conductive source electrode fingers of the primary transistor that are coupled to the shared metallization area; forming a set of two or more electrically conductive drain electrode fingers of the primary transistor in an interdigitated arrangement with the source electrode fingers; and forming a set of two or more electrically conductive gate metallization area fingers of the primary transistor that are disposed in an interdigitated arrangement with the source electrode fingers and the drain electrode fingers.