# US 12,119,296 B2 · Encircling a semiconductor device with stacked frames on a substrate > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,119,296 B2 - Document ID: US12119296B2 - Status: Granted - Kind: B2 - Application number: 18/363,766 - Filed: 2023-08-02 - Published: 2023-11-30 - Granted: 2024-10-15 - Earliest claimed: 2021-03-26 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Chien-Hung Chen; Shu-Shen Yeh; Yu-Sheng Lin; Po-Yao Lin; Shin-Puu Jeng - Web page: https://patentgrep.com/patent/US12119296B2 ## CPC - H10W 70/65: Shapes or dispositions of interconnections - H10W 90/00: Package configurations - H10P 72/18: {characterised by being specially adapted for supporting a single substrate or by comprising a stack of such individual supports} - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/611: {for connecting multiple chips together} - H10W 74/111: {the semiconductor body being completely enclosed} - H10W 76/12: characterised by their shape - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H05K 1/0271: {Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion} - H05K 2201/2018: Presence of a frame in a printed circuit or printed circuit assembly - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/635: {Through-vias} - H10W 70/698: Semiconductor materials that are electrically insulating, e.g. undoped silicon - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 76/40: Fillings or auxiliary members in containers, e.g. centering rings (fillings or auxiliary members for thermal protection or control in containers or encapsulations H10W40/70) - H10W 90/20: Configurations of stacked chips - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/732: {between stacked chips} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ## Abstract A semiconductor device includes a circuit substrate, at least one semiconductor die, a first frame, and a second frame. The at least one semiconductor die is connected to the circuit substrate. The first frame is disposed on the circuit substrate and encircles the at least one semiconductor die. The second frame is stacked on the first frame. The first frame includes a base portion and an overhang portion. The base portion has a first width. The overhang portion is disposed on the base portion and has a second width greater than the first width. The overhang portion laterally protrudes towards the at least one semiconductor die with respect to the base portion. The first width and the second width are measured in a protruding direction of the overhang portion. ## Claims ### Claim 1 A semiconductor device, comprising: a circuit substrate; at least one semiconductor die, connected to the circuit substrate; a first frame disposed on the circuit substrate and encircling the at least one semiconductor die; and a second frame stacked on the first frame, wherein the first frame comprises a base portion and an overhang portion laterally protrudes towards the at least one semiconductor die with respect to the base portion, and wherein the second frame laterally protrudes towards the at least one semiconductor die with respect to the overhang portion of the first frame. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein a sidewall of the first frame is flushed with a sidewall of the circuit substrate. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein a sidewall of the first frame is flushed with a sidewall of the second frame. ### Claim 4 (depends on 1) The semiconductor device of claim 1, further comprising a third frame disposed on the second frame, wherein a sidewall of the third frame is flushed with a sidewall of the second frame. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein the first frame comprises a first material different than a second material comprised in the second frame, a coefficient of thermal expansion of the first material is smaller than a coefficient of thermal expansion of the second material, and a third material comprised in the circuit substrate has a coefficient of thermal expansion intermediate between the first material and the second material. ### Claim 6 (depends on 1) The semiconductor device of claim 1, further comprising a surface mount device connected on the circuit substrate and disposed between the overhang portion of the first frame and the circuit substrate. ### Claim 7 (depends on 1) The semiconductor device of claim 1, further comprising a first adhesive adhering the first frame to the circuit substrate, and a second adhesive adhering the second frame to the first frame. ### Claim 8 A semiconductor device, comprising: a circuit substrate; a semiconductor package connected to the circuit substrate; a first metallic ring disposed on the circuit substrate and laterally surrounding the semiconductor package; and a second metallic ring disposed on the first metallic ring, wherein an outer sidewall of the first metallic ring is aligned with an outer sidewall of the second metallic ring, and an inner sidewall of the first metallic ring is misaligned with an inner sidewall of the second metallic ring. ### Claim 9 (depends on 8) The semiconductor device of claim 8, wherein the first metallic ring comprises a base portion and an overhang portion laterally protrudes towards the semiconductor package with respect to the base portion. ### Claim 10 (depends on 9) The semiconductor device of claim 9, wherein the overhang portion of the first metallic ring protrudes from the inner sidewall of the second metallic ring. ### Claim 11 (depends on 9) The semiconductor device of claim 9, wherein the inner sidewall of the second metallic ring protrudes from the overhang portion of the first metallic ring. ### Claim 12 (depends on 8) The semiconductor device of claim 8, further comprising a third metallic ring disposed on the second metallic ring, wherein the second metallic ring protrudes from the third metallic ring. ### Claim 13 (depends on 12) The semiconductor device of claim 12, wherein an outer sidewall of the third metallic ring is flushed with the outer sidewall of the second metallic ring. ### Claim 14 (depends on 8) The manufacturing method of claim 8, further comprising a third metallic ring disposed on the second metallic ring, wherein the third metallic ring protrudes from the inner sidewall of the second metallic ring. ### Claim 15 A manufacturing method of a semiconductor device, comprising: placing semiconductor dies side by side on a circuit substrate; and bonding an assembled frame ring to the circuit substrate, wherein the assembled frame ring encircles the semiconductor dies, and the assembled frame ring has a stepped sidewall towards the semiconductor dies. ### Claim 16 (depends on 15) The manufacturing method of claim 15, wherein bonding the assembled frame ring to the circuit substrate comprises: bonding a first frame ring to the circuit substrate, wherein the first frame ring encircles the semiconductor package; and bonding a second frame ring to the first frame ring. ### Claim 17 (depends on 16) The manufacturing method of claim 16, wherein the first frame ring comprises a base portion and an overhang portion laterally protrudes towards the semiconductor dies with respect to the base portion, and the second frame ring laterally protrudes towards the semiconductor dies with respect to the overhang portion of the first frame ring. ### Claim 18 (depends on 16) The manufacturing method of claim 16, further comprising, connecting a surface mount device to the circuit substrate before bonding the first frame ring, wherein the first frame ring is bonded to the circuit substrate so that the surface mount device is disposed below the at least one overhang of the first frame ring. ### Claim 19 (depends on 16) The manufacturing method of claim 16, further comprising bonding a third frame ring to the second frame ring, wherein the second frame ring has at least one protrusion with respect to the third frame ring. ### Claim 20 (depends on 16) The manufacturing method of claim 16, further comprising bonding a third frame ring to the second frame ring, wherein the third frame ring has at least one overhang towards the semiconductor dies with respect to the second frame ring.