# US 12,119,295 B2 · Wafer system-level three-dimensional fan-out three-dimensional fan-out packaging structure and manufacturing method thereof

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- Number: US 12,119,295 B2
- Document ID: US12119295B2
- Status: Granted
- Kind: B2
- Application number: 17/531,631
- Filed: 2021-11-19
- Published: 2022-05-26
- Granted: 2024-10-15
- Earliest claimed: 2020-11-20
- Assignees: SJ Semiconductor(Jiangyin) Corporation
- Applicants: Sj Semiconductor (Jiangyin) Corporation
- Inventors: Yenheng Chen; Chengchung Lin
- Web page: https://patentgrep.com/patent/US12119295B2

## CPC

- H10W 70/65: Shapes or dispositions of interconnections
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/095: {of vias therein}
- H10W 70/685: comprising multiple insulating layers
- H10W 74/47: comprising organic materials, e.g. plastics or resins
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10W 70/635: {Through-vias}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A wafer system-level three-dimensional fan-out packaging structure and a manufacturing method therefor. The method includes: forming a redistribution layer, where the redistribution layer includes a first surface and a second surface opposite to each other; forming a conductive connecting post on the second surface of the redistribution layer; bonding the patch element to the second surface of the redistribution layer; forming a plastic packaging layer on the second surface of the redistribution layer; thinning the plastic packaging layer; forming a plurality of solder bumps on a side of the plastic packaging layer that faces away from the redistribution layer; cutting the redistribution layer and the plastic packaging layer to obtain a number of first package structures; and bonding a second package layer to the first surface of the redistribution layer of one of the first package structures.

## Claims

### Claim 1

A method for manufacturing a wafer system-level three-dimensional fan-out packaging structure, comprising:
providing a carrier substrate having a release layer;
forming a redistribution layer on the release layer of the carrier substrate, wherein the redistribution layer comprises a first surface and a second surface opposite to each other, wherein the redistribution layer comprises at least one dielectric layer and at least one metal distribution layer that are stacked parallel to a top surface of the carrier substrate;
forming vias in the second surface of the redistribution layer, exposing the metal distribution layer;
forming a conductive connecting post in one of the vias, wherein the conductive connecting post is electrically connected to the redistribution layer;
forming two metal contacts in two of the vias respectively, wherein said two of the vias differ from the one of the vias connected to the conductive connecting post;
forming a patch element between the two metal contacts, wherein each of two sides of the patch element connects to one of the two metal contacts;
bonding the patch element to the second surface of the redistribution layer, wherein the patch element is electrically connected to the redistribution layer;
forming a plastic packaging layer on the second surface of the redistribution layer, wherein the plastic packaging layer covers the conductive connecting post and the patch element;
thinning the plastic packaging layer to expose the conductive connecting post;
forming solder bumps on a side of the plastic packaging layer that faces away from the redistribution layer, wherein one of the solder bumps is electrically connected to the conductive connecting post;
cutting the redistribution layer and the plastic packaging layer to obtain first package structures; and
providing a second package layer, and bonding the second package layer to the first surface of the redistribution layer on one of the first package structures, wherein the second package layer is electrically connected to the redistribution layer of one the first package structures.

### Claim 2 (depends on 1)

The method for manufacturing a wafer system-level three-dimensional fan-out packaging structure as in claim 1, wherein the first surface of the redistribution layer is disposed to the release layer.

### Claim 3 (depends on 2)

The method for manufacturing a wafer system-level three-dimensional fan-out packaging structure as in claim 2, wherein before the cutting, the carrier substrate and the release layer are removed to expose the first surface of the redistribution layer.

### Claim 4 (depends on 1)

The method for manufacturing a wafer system-level three-dimensional fan-out packaging structure as in claim 1, wherein each one of the vias extends from the first surface of the redistribution layer toward the at least one metal distribution layer of the redistribution layer to expose the at least one metal distribution layer.

### Claim 5 (depends on 4)

The method for manufacturing a wafer system-level three-dimensional fan-out packaging structure as in claim 4, wherein the vias are formed by laser drilling.

### Claim 6 (depends on 4)

The method for manufacturing a wafer system-level three-dimensional fan-out packaging structure as in claim 4, wherein conductive bumps are disposed on a side of the second package layer, wherein each of the conductive bumps extends into one of the vias to be electrically connected to the at least one metal distribution layer.

### Claim 7 (depends on 1)

The method for manufacturing a wafer system-level three-dimensional fan-out packaging structure as in claim 1, further comprising forming an insulating layer on the side of the plastic packaging layer that faces away from the redistribution layer, and forming an under-bump-metallization layer on a surface of the insulating layer, wherein the solder bumps are formed on a side of the under-bump-metallization layer that faces away from the plastic packaging layer.

### Claim 8 (depends on 1)

The method for manufacturing a wafer system-level three-dimensional fan-out packaging structure as in claim 1, wherein the patch element comprises a passive electrical element.