# US 12,119,288 B2 · Semiconductor package

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- Number: US 12,119,288 B2
- Document ID: US12119288B2
- Status: Granted
- Kind: B2
- Application number: 17/658,614
- Filed: 2022-04-08
- Published: 2022-12-29
- Granted: 2024-10-15
- Earliest claimed: 2021-06-29
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Youngbae Kim; Sungwoo Park
- Web page: https://patentgrep.com/patent/US12119288B2

## CPC

- H10W 70/415: {Leadframe inner leads serving as die pads}
- H10W 70/421: {Shapes or dispositions}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 70/042: {Etching}
- H10W 70/417: {Bonding materials between chips and die pads}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes: a lead frame that includes a first surface and a second surface opposite to the first surface, where the lead frame includes a first lead that extends in a first direction, and a plurality of second leads that are spaced apart from the first lead on both sides of the first lead; at least one semiconductor chip mounted on the first surface of the lead frame by a plurality of bumps; and an encapsulant that encapsulates the lead frame and the at least one semiconductor chip, wherein the first lead has a groove in the first surface that partitions the plurality of bumps in contact with the first lead.

## Claims

### Claim 1

A semiconductor package, comprising:
a lead frame that includes a first surface and a second surface opposite to the first surface, wherein the lead frame further includes a first lead that extends in a first direction, and a plurality of second leads that are spaced apart from the first lead on both sides of the first lead;
at least one semiconductor chip mounted on the first surface of the lead frame by a plurality of bumps; and
an encapsulant that encapsulates the lead frame and the at least one semiconductor chip,
wherein the first lead has a groove in the first surface that partitions the plurality of bumps in contact with the first lead, wherein the groove comprises,
a first groove disposed in the first lead and that extends in the first direction; and
a plurality of second grooves that extend from the first groove in a second direction that is perpendicular to the first direction,
wherein the first groove and each of the second grooves is spaced apart from an outer side surface of the first lead,
wherein first groove partitions the plurality of bumps in the first direction, and the second grooves partition the plurality of bumps in the second direction.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein a volume of the groove is from 15% to 30% of a volume of the first lead.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein the groove has a depth of from ⅓ to ½ of a thickness of the first lead.

### Claim 4 (depends on 1)

The semiconductor package of claim 1, wherein the first groove is disposed along a center in a width direction of the first lead.

### Claim 5 (depends on 1)

The semiconductor package of claim 1, wherein
the plurality of second grooves comprise a first group disposed adjacent to both ends of the first lead, and a second group other than the first group, and
a length of the first group is greater than a length of the second group.

### Claim 6 (depends on 1)

The semiconductor package of claim 1, wherein
the plurality of second grooves comprises a first group disposed adjacent to both ends of the first lead, and a second group other than the first group, and
a width of the first group is greater than a width of the second group.

### Claim 7 (depends on 1)

The semiconductor package of claim 1, wherein
the encapsulant includes first and second sides that face each other and third and fourth sides that connect the first and second sides, wherein the encapsulant forms a bottom surface of the semiconductor package,
wherein the second surface of the lead frame is exposed by the bottom surface.

### Claim 8 (depends on 7)

The semiconductor package of claim 7,
wherein the first lead connects the first and second sides,
wherein the plurality of second leads are in contact with at least one of the first to fourth sides.

### Claim 9 (depends on 8)

The semiconductor package of claim 8, wherein the first lead connects a center of the first side and a center of the second side.