# US 12,119,286 B2 · Die, memory and method of manufacturing die

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- Number: US 12,119,286 B2
- Document ID: US12119286B2
- Status: Granted
- Kind: B2
- Application number: 17/647,883
- Filed: 2022-01-13
- Published: 2022-11-24
- Granted: 2024-10-15
- Earliest claimed: 2021-05-19
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: ChihCheng Liu
- Web page: https://patentgrep.com/patent/US12119286B2

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10W 20/01: {Manufacture or treatment}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/4421: {the principal metal being copper}
- H10W 20/4441: {the principal metal being a refractory metal}
- H10W 90/00: Package configurations
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A die, a memory and a method of manufacturing the die are provided. The die includes a substrate and a conductive structure, where the substrate has an interconnection structure layer, the conductive structure includes a first conductive structure and a second conductive structure connected with the first conductive structure, the first conductive structure is connected with the interconnection structure layer, and a coefficient of thermal expansion of the first conductive structure is smaller than that of copper.

## Claims

### Claim 1

A die, comprising:
a substrate, wherein an interconnection structure layer is arranged on the substrate; and
a conductive structure arranged within the substrate, wherein the conductive structure comprises a first conductive structure and a second conductive structure connected with the first conductive structure, the first conductive structure is connected with the interconnection structure layer, a coefficient of thermal expansion of the first conductive structure is smaller than a coefficient of thermal expansion of copper, and a coefficient of thermal expansion of the second conductive structure is smaller than the coefficient of thermal expansion of copper.

### Claim 2 (depends on 1)

The die according to claim 1, wherein the first conductive structure is arranged within the second conductive structure, a top surface of the first conductive structure is flush with a top surface of the second conductive structure, and a material of the second conductive structure is same as a material of the first conductive structure.

### Claim 3 (depends on 2)

The die according to claim 2, wherein the first conductive structure comprises a plurality of cylindrical bodies arranged at intervals, and axes of the plurality of cylindrical bodies are perpendicular to the substrate.

### Claim 4 (depends on 3)

The die according to claim 3, wherein by taking a plane parallel to the substrate as a cross section, cross sections of the plurality of cylindrical bodies are circular or polygonal.

### Claim 5 (depends on 2)

The die according to claim 2, wherein the first conductive structure comprises a first strip-shaped body and a second strip-shaped body intersected with the first strip-shaped body, and both a depth direction of the first strip-shaped body and a depth direction of the second strip-shaped body are perpendicular to the substrate.

### Claim 6 (depends on 5)

The die according to claim 5, wherein the first strip-shaped body extends along a first direction, the second strip-shaped body extends along a second direction, and the first direction is intersected with the second direction.

### Claim 7 (depends on 6)

The die according to claim 6, wherein the first direction and the second direction are perpendicular to each other.

### Claim 8 (depends on 7)

The die according to claim 7, wherein there are a plurality of first strip-shaped bodies and the plurality of first strip-shaped bodies are arranged at intervals along the second direction; and
there are a plurality of second strip-shaped bodies and the plurality of second strip-shaped bodies are arranged at intervals along the first direction.

### Claim 9 (depends on 8)

The die according to claim 8, wherein by taking a plane perpendicular to the substrate as a longitudinal section, both longitudinal sections of the plurality of first strip-shaped bodies and the plurality of second strip-shaped bodies are rectangular.

### Claim 10 (depends on 1)

The die according to claim 1, wherein an intermetallic dielectric layer is further arranged on the substrate, the first conductive structure is arranged within the intermetallic dielectric layer, and one part of the second conductive structure is arranged within the substrate while a second part of the second conductive structure is arranged within the intermetallic dielectric layer.

### Claim 11 (depends on 1)

A memory, comprising a plurality of dies according to claim 1, wherein the plurality of dies are stacked in sequence, and two adjacent layers of dies are connected through the interconnection structure layer.

### Claim 12

A method of manufacturing a die, comprising:
providing a substrate, wherein an intermetallic dielectric layer is arranged on the substrate, and an etching stop layer is arranged within the intermetallic dielectric layer;
forming a first conductive structure within the intermetallic dielectric layer, wherein a bottom of the first conductive structure is in contact with the etching stop layer, and a coefficient of thermal expansion of the first conductive structure is smaller than a coefficient of thermal expansion of copper;
forming an interconnection structure layer on the intermetallic dielectric layer, wherein the interconnection structure layer is connected with one end of the first conductive structure away from the substrate; and
forming a second conductive structure within the substrate, wherein the second conductive structure extends into the intermetallic dielectric layer and is connected with the first conductive structure.

### Claim 13 (depends on 12)

The method of manufacturing a die according to claim 12, wherein the forming a first conductive structure within the intermetallic dielectric layer comprises:
forming a filling region within the intermetallic dielectric layer, wherein a bottom surface of the filling region is flush with a top surface of the etching stop layer; and
forming the first conductive structure within the filling region, wherein a material of the first conductive structure comprises tungsten.

### Claim 14 (depends on 13)

The method of manufacturing a die according to claim 13, wherein the forming a filling region within the intermetallic dielectric layer comprises:
forming a plurality of filling holes arranged at intervals within the intermetallic dielectric layer, wherein an axis of each of the plurality of filling holes is perpendicular to the substrate, the plurality of filling holes expose the top surface of the etching stop layer, and the plurality of filling holes form the filling region.

### Claim 15 (depends on 14)

The method of manufacturing a die according to claim 14, wherein the forming the first conductive structure within the filling region comprises:
forming a cylindrical body in each of the plurality of filling holes, wherein a plurality of cylindrical bodies form the first conductive structure.

### Claim 16 (depends on 13)

The method of manufacturing a die according to claim 13, wherein the forming a filling region within the intermetallic dielectric layer comprises:
forming a first filling slot extending along a first direction and a second filling slot extending along a second direction within the intermetallic dielectric layer, wherein the first direction is intersected with the second direction, both a bottom of the first filling slot and a bottom of the second filling slot are the top surface of the etching stop layer, and the first filling slot and the second filling slot form the filling region.

### Claim 17 (depends on 16)

The method of manufacturing a die according to claim 16, wherein the forming a first filling slot extending along a first direction and a second filling slot extending along a second direction within the intermetallic dielectric layer comprises:
forming a plurality of first filling slots and a plurality of second filling slots within the intermetallic dielectric layer, wherein the plurality of first filling slots are arranged at intervals along the second direction, and the plurality of second filling slots are arranged at intervals along the first direction.

### Claim 18 (depends on 17)

The method of manufacturing a die according to claim 17, wherein the forming the first conductive structure within the filling region comprises:
forming first strip-shaped bodies within the plurality of first filling slots and forming second strip-shaped bodies within the plurality of second filling slots, wherein the first strip-shaped bodies and the second strip-shaped bodies form the first conductive structure.

### Claim 19 (depends on 12)

The method of manufacturing a die according to claim 12, wherein the forming a second conductive structure within the substrate comprises:
forming a first intermediate hole within the substrate, wherein a bottom wall of the first intermediate hole is a top surface of the substrate;
forming an initial oxide layer and an initial barrier layer that are stacked on a side wall and the bottom wall of the first intermediate hole, wherein the initial barrier layer located within the first intermediate hole forms a second intermediate hole;
removing the initial oxide layer and the initial barrier layer that are located on a bottom wall of the second intermediate hole, and removing the intermetallic dielectric layer exposed inside the second intermediate hole, so as to form a third intermediate hole within the intermetallic dielectric layer, wherein the third intermediate hole exposes outer surfaces of the first conductive structure and the etching stop layer, and a retained portion of the initial oxide layer forms an oxide layer while a retained portion of the initial barrier layer forms a barrier layer; and
forming the second conductive structure within the second intermediate hole and the third intermediate hole, wherein a material of the second conductive structure comprises copper.