# US 12,119,284 B2 · DBC substrate for power semiconductor devices, method for fabricating a DBC substrate and power semiconductor device having a DBC substrate > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,119,284 B2 - Document ID: US12119284B2 - Status: Granted - Kind: B2 - Application number: 17/690,616 - Filed: 2022-03-09 - Published: 2022-09-22 - Granted: 2024-10-15 - Earliest claimed: 2021-03-22 - Assignees: Infineon Technologies Austria AG - Applicants: Infineon Technologies Austria AG - Inventors: Alexander Roth - Web page: https://patentgrep.com/patent/US12119284B2 ## CPC - H10W 40/255: {having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates} - C04B 37/023: {characterised by the interlayer used (C04B37/028 takes precedence)} - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/69: Insulating materials thereof - H10W 70/692: Ceramics or glasses - H10W 72/30: Die-attach connectors - C04B 2237/121: based on aluminium - C04B 2237/124: based on copper - C04B 2237/36: Non-oxidic - C04B 2237/361: Boron nitride - C04B 2237/365: Silicon carbide - C04B 2237/366: Aluminium nitride - C04B 2237/368: Silicon nitride - C04B 2237/407: Copper - C04B 2237/704: of one or more of the ceramic layers or articles - C04B 2237/706: of one or more of the metallic layers or articles - C04B 2237/708: of one or more of the interlayers - C04B 2237/72: Forming laminates or joined articles comprising at least two interlayers directly next to each other - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - C04B: LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE {(roofing granules E04D7/005)}; CERAMICS (devitrified glass-ceramics C03C10/00); REFRACTORIES; TREATMENT OF NATURAL STONE ## Abstract A DBC substrate for power semiconductor devices includes a ceramic workpiece of a non-oxide ceramic having first and second opposing main sides, the ceramic workpiece having a thickness of 10 μm or more measured between the first and second main sides, a copper-containing layer disposed over the first main side, the copper-containing layer having a thickness of 5 μm or more, and an intermediate layer comprising Al2O3 disposed between the ceramic workpiece and the copper-containing layer. ## Claims ### Claim 1 A DBC substrate for power semiconductor devices, the DBC substrate comprising: a ceramic workpiece of a non-oxide ceramic having a first main side and an opposing second main side, the ceramic workpiece having a thickness of 10 μm or more measured between the first and second main sides; a copper-containing layer disposed over the first main side, the copper-containing layer having a thickness of 5 μm or more; and an intermediate layer comprising one or more monolayers of Al2O3 disposed between the ceramic workpiece and the copper-containing layer, wherein the intermediate layer further comprises CuAl2O4 arranged between the copper-containing layer and the one or more monolayers of Al2O3. ### Claim 2 (depends on 1) The DBC substrate of claim 1, wherein the CuAl2O4 comprises 1 to 30 monolayers of CuAl2O4 arranged between the copper-containing layer and the one or more monolayers of Al2O3. ### Claim 3 (depends on 1) The DBC substrate of claim 1, wherein the ceramic workpiece further comprises lateral sides connecting the first and second main sides, the lateral sides being free of the copper-containing layer. ### Claim 4 (depends on 1) The DBC substrate of claim 1, wherein the copper-containing layer is patterned to comprise connection regions and/or conductive tracks electrically isolated from each other, and wherein the intermediate layer is also disposed in trenches between the connection regions and/or the conductive tracks. ### Claim 5 (depends on 1) The DBC substrate of claim 1, wherein the ceramic workpiece has cooling fins on the second main side. ### Claim 6 (depends on 1) The DBC substrate of claim 1, wherein the intermediate layer comprises 5 to 50 monolayers of Al2O3. ### Claim 7 (depends on 6) The DBC substrate of claim 6, wherein the intermediate layer comprises 10 to 30 monolayers of Al2O3. ### Claim 8 (depends on 1) The DBC substrate of claim 1, wherein the ceramic workpiece comprises one or more of Si3Ni4, AlN, BN, SiC and BC. ### Claim 9 A method for fabricating a DBC substrate, the method comprising: providing a ceramic workpiece of a non-oxide ceramic having a first main side and an opposing second main side, the ceramic workpiece having a thickness of 10 μm or greater measured between the first and second main sides; depositing one or more aluminum-containing monolayers on at least the first main side of the ceramic workpiece by atomic layer deposition; and depositing a copper-containing layer over the one or more aluminum-containing monolayers by a direct bonded copper process, wherein 5 to 50 aluminum-containing monolayers are deposited. ### Claim 10 (depends on 9) The method of claim 9, further comprising: depositing one or more copper-containing monolayers on the one or more aluminum-containing monolayers by atomic layer deposition. ### Claim 11 (depends on 10) The method of claim 10, wherein 5 to 50 copper-containing monolayers are deposited. ### Claim 12 (depends on 9) The method of claim 9, wherein the ceramic workpiece comprises one or more of Si3Ni4, AlN, BN, SiC and BC. ### Claim 13 (depends on 9) The method of claim 9, further comprising: after performing the direct bonded copper process, patterning the copper-containing layer to create connection regions and/or conductive tracks. ### Claim 14 (depends on 13) The method of claim 13, wherein the DBC substrate is produced as part of a composite in a batch process, the method further comprising: separating the composite into a plurality of DBC substrates. ### Claim 15 (depends on 9) The method of claim 9, wherein the aluminum-containing monolayers comprise Al2O3. ### Claim 16 A power semiconductor device, comprising: a DBC substrate comprising a ceramic workpiece of a non-oxide ceramic having a first main side and an opposing second main side, the ceramic workpiece having a thickness of 10 μm or more measured between the first and second main sides, a copper-containing layer disposed over the first main side, the copper-containing layer having a thickness of 5 μm or more, and an intermediate layer comprising one or more monolayers of Al2O3 disposed between the ceramic workpiece and the copper-containing layer; and a power semiconductor chip disposed on the DBC substrate and electrically connected thereto, wherein the intermediate layer further comprises CuAl2O4 arranged between the copper-containing layer and the one or more monolayers of Al2O3. ### Claim 17 (depends on 16) The power semiconductor device of claim 16, wherein the DBC substrate is configured for direct liquid cooling. ### Claim 18 (depends on 1) The DBC substrate of claim 1, further comprising: one or more copper-containing monolayers deposited on the one or more one or more monolayers of Al2O3 by atomic layer deposition.