# US 12,119,282 B2 · Method of making a semiconductor device package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,119,282 B2 - Document ID: US12119282B2 - Status: Granted - Kind: B2 - Application number: 17/876,468 - Filed: 2022-07-28 - Published: 2022-11-17 - Granted: 2024-10-15 - Earliest claimed: 2018-09-07 - Assignees: Advanced Semiconductor Engineering, Inc. - Applicants: Advanced Semiconductor Engineering, Inc. - Inventors: Tun-Ching Pi; Yen-Chi Huang; Hao-Chih Hsieh; Jin Han Shih - Web page: https://patentgrep.com/patent/US12119282B2 ## CPC - H10W 74/114: {by a substrate and the encapsulations} - H10W 74/131: {the semiconductor body being only partially enclosed} - H05K 1/185: associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards - H05K 3/284: {for encapsulating mounted components (H05K1/185 takes precedence)} - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/68: Shapes or dispositions thereof - H10W 74/01: Manufacture or treatment - H10W 74/016: {using moulds} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H05K 2201/09036: Recesses or grooves in insulating substrate - H05K 2201/09045: Locally raised area or protrusion of insulating substrate - H05K 2201/09127: PCB or component having an integral separable or breakable part - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/10: characterised by their shape or disposition - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ## Abstract A semiconductor device package includes a carrier and an encapsulant disposed on the carrier. At least one portion of the encapsulant is spaced from the carrier by a space. ## Claims ### Claim 1 A method of manufacturing a semiconductor device package, comprising: providing a substrate with a recess and an electronic component, wherein the electronic component is disposed over the substrate and outside the recess; forming a sacrificial material over the recess of the substrate; encapsulating the substrate and the sacrificial material by an encapsulant; removing a portion of the encapsulant to expose the sacrificial material; removing the sacrificial material; and after removing the sacrificial material, forming a concave recessed from a lower surface of the encapsulant, wherein the concave is in communication with an outside of the semiconductor device package through the recess; wherein the concave horizontally overlaps the electronic component. ### Claim 2 (depends on 1) The method of claim 1, further comprising: exposing a first inclined lateral surface of the encapsulant after removing the portion of the encapsulant. ### Claim 3 (depends on 2) The method of claim 2, wherein the first inclined lateral surface vertically overlaps the recess. ### Claim 4 (depends on 2) The method of claim 2, further comprising: exposing a second inclined lateral surface of the encapsulant after removing the portion of the encapsulant; wherein an extending direction of the second inclined lateral surface is different from an extending direction of the first inclined lateral surface. ### Claim 5 (depends on 4) The method of claim 4, wherein a horizontal distance between the first inclined lateral surface and the second inclined lateral surface is tapered toward the substrate. ### Claim 6 (depends on 1) The method of claim 1, wherein a width of the recess is greater than a width of the concave. ### Claim 7 (depends on 1) The method of claim 1, further comprising: encapsulating the electronic component by the encapsulant while encapsulating the substrate and the sacrificial material by the encapsulant. ### Claim 8 (depends on 7) The method of claim 7, wherein the encapsulant comprises a first portion between the electronic component and the substrate. ### Claim 9 (depends on 8) The method of claim 8, wherein the encapsulant comprises a second portion over the electronic component, and wherein a thickness of the second portion of the encapsulant is greater than a thickness of the first portion of the encapsulant. ### Claim 10 (depends on 7) The method of claim 7, wherein the electronic component comprises a first side and a second side opposite to the first side, wherein the first side of the electronic component is closer to the recess than the second side of the electronic component is, wherein the encapsulant has a third portion adjacent to the first side of the electronic component and a fourth portion adjacent to the second side of the electronic component, wherein a width of the third portion of the encapsulant is different from a width of the fourth portion of the encapsulant. ### Claim 11 (depends on 1) The method of claim 1, further comprising: forming the sacrificial material on an upper surface of the substrate while forming the sacrificial material over the substrate, wherein a level of an upper surface of the sacrificial material is lower than a level of an upper surface of the electronic component. ### Claim 12 (depends on 11) The method of claim 11, wherein the level of the upper surface of the sacrificial material is higher than a level of a lower surface of the electronic component with respect to the substrate.