# US 12,119,280 B2 · Semiconductor device package with reduced stress

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- Number: US 12,119,280 B2
- Document ID: US12119280B2
- Status: Granted
- Kind: B2
- Application number: 17/723,439
- Filed: 2022-04-18
- Published: 2022-08-04
- Granted: 2024-10-15
- Earliest claimed: 2020-03-20
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Gregory Thomas Ostrowicki; Amit Sureshkumar Nangia
- Web page: https://patentgrep.com/patent/US12119280B2

## CPC

- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 70/417: {Bonding materials between chips and die pads}
- H10W 70/465: {Bumps or wires}
- H10W 70/479: {on or in insulating or insulated package substrates, interposers, or redistribution layers}
- H10W 72/0198: {batch processes}
- H10W 72/075: {of bond wires}
- H10W 72/50: Bond wires
- H10W 74/014: {using batch processing}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 76/40: Fillings or auxiliary members in containers, e.g. centering rings (fillings or auxiliary members for thermal protection or control in containers or encapsulations H10W40/70)
- H10W 72/073: {of die-attach connectors}
- H10W 72/07304: {the auxiliary member being temporary, e.g. a sacrificial coating}
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A described example includes: a semiconductor device die with an active surface; the semiconductor device die mounted on a package substrate with substrate leads and the semiconductor device die electrically coupled to the substrate leads; at least a first rigid low expansion material (RLEM) covering a portion of the semiconductor device die; and the first RLEM, the semiconductor device die, and a portion of the substrate leads covered with mold compound and forming a packaged semiconductor device die.

## Claims

### Claim 1

An apparatus, comprising:
a semiconductor device die with an active surface;
the semiconductor device die mounted on a package substrate with substrate leads and the semiconductor device die electrically coupled to the substrate leads;
at least a first rigid low expansion material (RLEM) covering a portion of the semiconductor device die; and
the first RLEM, the semiconductor device die, and a portion of the substrate leads covered with a mold compound and forming a packaged semiconductor device die; and p1 a second RLEM with a first side over a non-device side of the semiconductor device die, wherein the first RLEM and the second RLEM are of a same material, and wherein the first RLEM and the second RLEM physically contact the semiconductor device die without any intervening layers.

### Claim 2 (depends on 1)

The apparatus of claim 1, further comprising:
a stress sensitive component on a device side of the semiconductor device die; and
the first RLEM covering the stress sensitive component.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the first RLEM covers a portion of a non-device side of the semiconductor device die.

### Claim 4 (depends on 2)

The apparatus of claim 2, wherein the stress sensitive component on the semiconductor device die is selected from a group consisting essentially of: a bipolar junction transistor (BJT), an analog transistor, an oscillator, a bulk acoustic wave (BAW) oscillator, a piezoelectric device, a junction field effect transistor (JFET), a metal oxide semiconductor field effect transistor (MOSFET), a thin film resistor, and a vertical capacitor.

### Claim 5 (depends on 1)

The apparatus of claim 1, further comprising
at least one stress sensitive component on the semiconductor device die;
the at least one stress sensitive component covered by the first RLEM; and
edges of the first RLEM overlapping the at least one stress sensitive component by at least 10 μm.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein a coefficient of thermal expansion of the first RLEM and the second RLEM is between about positive 2 ppm/° C. and negative 30 ppm/° C.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein a coefficient of thermal expansion of the first RLEM and the second RLEM is less than 2.6 ppm/° C.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the first RLEM and the second RLEM are one selected from a group consisting essentially of: sitall, invar, quartz, diamond, graphite, Corning ULE 7972, and Corning ULE 7973.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein wire bonds electrically couple the semiconductor device die to the substrate leads.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein a conductive post connects electrically couple the semiconductor device die to the substrate leads.

### Claim 11 (depends on 1)

The apparatus of claim 1, wherein solder ball bonds couple the semiconductor device die to the package substrate.

### Claim 12 (depends on 1)

The apparatus of claim 1, wherein the package substrate is a lead frame.

### Claim 13

A packaged semiconductor device, comprising:
a semiconductor device die with a device side and a non device side, the semiconductor device die mounted on a package substrate with substrate leads and the semiconductor device die electrically coupled to the substrate leads;
a first material including ceramic covering a stress sensitive component in a portion of the active surface of the semiconductor device die;
a second material including ceramic covering a non device side of the semiconductor device die; and
the first material, the second material, the semiconductor device die, and a portion of the substrate leads covered with a mold compound, wherein the first material and the second material are of a same material, and wherein the first material and the second material physically contact the semiconductor device die without any intervening layers.

### Claim 14 (depends on 13)

The packaged semiconductor device of claim 13, wherein the semiconductor device die is selected from a group consisting essentially of: a bipolar junction transistor (BJT), an analog transistor, an oscillator, a bulk acoustic wave (BAW) oscillator, a piezoelectric device, a junction field effect transistor (JFET), a metal oxide semiconductor field effect transistor (MOSFET), a thin film resistor, and a vertical capacitor.

### Claim 15 (depends on 13)

The packaged semiconductor device of claim 13, wherein a coefficient of thermal expansion of the first material and the second material is between about positive 2 ppm/° C. and negative 30 ppm/° C.

### Claim 16 (depends on 13)

The packaged semiconductor device of claim 13, wherein a coefficient of thermal expansion of the first material and the second material is less than 2.6 ppm/° C.

### Claim 17 (depends on 13)

The packaged semiconductor device of claim 13, wherein wire bonds electrically couple the semiconductor device die to the substrate leads.

### Claim 18 (depends on 13)

The packaged semiconductor device of claim 13, wherein the package substrate is a lead frame.