Latch-up test structure

A latch-up test structure, comprising:

• a substrate of a first conductive type;
• a first well region of the first conductive type, located in the substrate of the first conductive type;
• a first doped region of the first conductive type, located in the first well region of the first conductive type;
• a first doped region of a second conductive type, located in the first well region of the first conductive type and spaced apart from the first doped region of the first conductive type;
• and
• a second doped region of the first conductive type, a second doped region of the second conductive type, a third doped region of the first conductive type, and a third doped region of the second conductive type that are arranged at intervals in the substrate of the first conductive type;
• wherein the second doped region of the first conductive type, the second doped region of the second conductive type, the third doped region of the first conductive type, and the third doped region of the second conductive type are all located at a side of the first doped region of the second conductive type away from the first doped region of the first conductive type;
• and the second doped region of the first conductive type, the second doped region of the second conductive type, the third doped region of the first conductive type, and the third doped region of the second conductive type are each spaced apart from the first well region of the first conductive type;
• a first well region of the second conductive type, located in the substrate of the first conductive type;
• wherein the third doped region of the first conductive type and the third doped region of the second conductive type are both located in the first well region of the second conductive type, and the third doped region of the first conductive type is located between the third doped region of the second conductive type and the first well region of the first conductive type;
• the second doped region of the first conductive type is located between the first well region of the second conductive type and the first well region of the first conductive type, and is spaced apart from the first well region of the second conductive type and the first well region of the first conductive type;
• and
• a second well region of the second conductive type, located in the substrate of the first conductive type and between the first well region of the second conductive type and the second doped region of the first conductive type, and spaced apart from the first well region of the second conductive type and the second doped region of the first conductive type;
• wherein the second doped region of the second conductive type is located in the second well region of the second conductive type;
• wherein a first electrode is provided on an upper surface of the first doped region of the second conductive type;
• and a second electrode is provided on an upper surface of the first doped region of the first conductive type;
• the first doped region of the second conductive type, the first well region of the first conductive type, and the second well region of the second conductive type jointly form a first bipolar junction transistor (BJT);
• the second well region of the second conductive type, the substrate of the first conductive type, and the first well region of the second conductive type jointly form a second BJT;
• and the third doped region of the first conductive type, the first well region of the second conductive type, and the substrate of the first conductive type jointly form a third BJT.