# US 12,119,271 B1 · Backside gate contact, backside gate etch stop layer, and methods of forming same

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- Number: US 12,119,271 B1
- Document ID: US12119271B1
- Status: Granted
- Kind: B1
- Application number: 18/545,337
- Filed: 2023-12-19
- Granted: 2024-10-15
- Earliest claimed: 2023-12-19
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yi-Bo Liao; Wei-De Ho; Cheng-Ting Chung; Szuya Liao
- Web page: https://patentgrep.com/patent/US12119271B1

## CPC

- H10D 86/60: wherein the TFTs are in active matrices
- H10D 30/0198: {forming source or drain electrodes wherein semiconductor bodies are replaced by dielectric layers and the source or drain electrodes extend through the dielectric layers}
- H10D 30/026: {having laterally-coplanar source and drain regions, a gate at the sides of the bulk channel, and both horizontal and vertical current flow (of LDMOS H10D30/0289)}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 86/0214: {using temporary substrates}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method includes forming a first transistor and a second transistor over a semiconductor substrate, wherein the first transistor and the second transistor are vertically stacked. The method further includes exposing a backside of a first gate stack of the first transistor; forming a backside gate etch stop layer (ESL) on the backside of the first gate stack; patterning a contact opening through the backside gate ESL to expose the first gate stack; and forming a backside gate contact in the contact opening. The backside gate contact extends through the backside gate ESL to electrically connect to the first gate stack.

## Claims

### Claim 1

A method comprising:
forming a first transistor and a second transistor over a semiconductor substrate, wherein the first transistor and the second transistor are vertically stacked;
exposing a backside of a first gate stack of the first transistor, wherein exposing the backside of the first gate stack comprises removing the semiconductor substrate;
forming a backside gate etch stop layer (ESL) on the backside of the first gate stack;
patterning a contact opening through the backside gate ESL to expose the first gate stack; and
forming a backside gate contact in the contact opening, wherein the backside gate contact extends through the backside gate ESL to electrically connect to the first gate stack.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first gate stack comprises a gate dielectric and a gate electrode, and wherein forming the backside gate ESL comprises blanket depositing the backside gate ESL over the gate dielectric.

### Claim 3 (depends on 2)

The method of claim 2 further comprising blanket depositing an additional ESL on a surface of the backside gate ESL opposite to the first transistor, wherein patterning the contact opening comprises patterning the contact opening through the additional ESL and the gate dielectric.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first gate stack comprises a gate dielectric and a gate electrode, and wherein forming the backside gate ESL comprises selectively depositing the backside gate ESL on the gate electrode.

### Claim 5 (depends on 4)

The method of claim 4, wherein exposing the backside of the first gate stack further comprises defining an opening in a shallow trench isolation (STI) region by removing a semiconductor fin, wherein the method further comprises:
removing a portion of the gate dielectric exposed by the opening in the STI region, wherein forming the backside gate ESL comprises selectively depositing the backside gate ESL in the opening.

### Claim 6 (depends on 1)

The method of claim 1, wherein the backside gate ESL comprises a metal or a metal oxide, wherein the first transistor comprises a plurality of nanostructures, and wherein patterning the contact opening comprises patterning the contact opening in a location that overlaps the plurality of nanostructures.

### Claim 7

A method comprising:
forming a multi-layer stack over a semiconductor substrate, the multi-layer stack comprising alternating semiconductor nanostructures and dummy nanostructures;
forming lower source/drain regions, wherein lower semiconductor nanostructures of the semiconductor nanostructures extend between the lower source/drain regions;
forming upper source/drain regions over the lower source/drain regions, wherein upper semiconductor nanostructures of the semiconductor nanostructures extend between the upper source/drain regions;
replacing the dummy nanostructures with a lower gate stack around the lower semiconductor nanostructures and an upper gate stack around the upper semiconductor nanostructures;
exposing a backside of the lower gate stack;
depositing a metal-comprising backside gate etch stop layer (ESL) on the backside of the lower gate stack; and
forming a backside gate contact extending through the metal-comprising backside gate ESL to electrically connect to the lower gate stack, wherein the backside gate contact overlaps the lower semiconductor nanostructures and the upper semiconductor nanostructures.

### Claim 8 (depends on 7)

The method of claim 7, wherein depositing the metal-comprising backside gate ESL comprises a blanket deposition process.

### Claim 9 (depends on 7)

The method of claim 7, wherein depositing the metal-comprising backside gate ESL comprises a selective deposition process.

### Claim 10 (depends on 7)

The method of claim 7 further comprising depositing a dielectric ESL over the metal-comprising backside gate ESL, wherein forming the backside gate contact comprises forming the backside gate contact to extend through the dielectric ESL.

### Claim 11 (depends on 7)

The method of claim 7, wherein the metal-comprising backside gate ESL is made of aluminum oxide, hafnium silicon oxide, or zirconium oxide.

### Claim 12 (depends on 7)

The method of claim 7, wherein a thickness of the metal-comprising backside gate ESL is at least 2 nm.

### Claim 13 (depends on 7)

The method of claim 7, wherein exposing the backside of the lower gate stack comprises removing the semiconductor substrate.

### Claim 14

A method comprising:
forming a device layer on a semiconductor substrate, the device layer comprising:
a plurality of first nanostructures, the plurality of first nanostructures extending between first source/drain regions;
a plurality of second nanostructures over the plurality of first nanostructures, the plurality of second nanostructure extending between second source/drain regions;
a first gate stack around the plurality of first nanostructures; and
a second gate stack around the plurality of second nanostructures, wherein the first gate stack is vertically stacked with the second gate stack;
removing the semiconductor substrate to expose a backside of the first gate stack;
depositing a backside gate etch stop layer (ESL) on the backside of the first gate stack, wherein the backside gate ESL comprises a metal; and
patterning an opening through the backside gate ESL, wherein the opening exposes one of the first source/drain regions; and
filling the opening with a conductive material.

### Claim 15 (depends on 14)

The method of claim 14, wherein the backside gate ESL is made of aluminum oxide, hafnium silicon oxide, or zirconium oxide, and wherein a thickness of the backside gate ESL is at least 2 nm.

### Claim 16 (depends on 14)

The method of claim 14, further comprising depositing an additional etch stop layer (ESL) over and in direct contact with the backside gate ESL, wherein patterning the opening comprises patterning the opening through the additional ESL.

### Claim 17 (depends on 14)

The method of claim 14, wherein patterning the opening comprises patterning the opening to overlap the plurality of first nanostructures.

### Claim 18 (depends on 14)

The method of claim 14, wherein depositing the backside gate ESL comprises depositing the backside gate ESL in direct contact with a gate dielectric of the first gate stack.

### Claim 19 (depends on 18)

The method of claim 18, wherein patterning the opening comprises patterning the opening through the gate dielectric of the first gate stack.

### Claim 20 (depends on 18)

The method of claim 18, wherein depositing the backside gate ESL comprises a blanket deposition process.