# US 12,119,269 B2 · Array of vertical transistors having channel regions connected by an elongated conductor line

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- Number: US 12,119,269 B2
- Document ID: US12119269B2
- Status: Granted
- Kind: B2
- Application number: 17/824,744
- Filed: 2022-05-25
- Published: 2022-09-22
- Granted: 2024-10-15
- Earliest claimed: 2019-09-03
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Deepak Chandra Pandey; Haitao Liu; Kamal M. Karda
- Web page: https://patentgrep.com/patent/US12119269B2

## CPC

- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 84/016: {the components including vertical IGFETs}
- H10B 12/05: {Making the transistor}
- H10B 12/31: {having a storage electrode stacked over the transistor}
- H10B 12/395: {the transistor being vertical}
- H10B 51/30: characterised by the memory core region
- H10B 53/30: characterised by the memory core region
- H10B 63/34: {of the vertical channel field-effect transistor type}
- H10B 99/00: Subject matter not provided for in other groups of this subclass
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/6728: {Vertical TFTs}
- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0195: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/837: {comprising vertical IGFETs}
- H10W 20/43: Layouts of interconnections
- H10P 50/283: {by chemical means}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An array of vertical transistors comprises spaced pillars individually comprising a channel region of individual vertical transistors. A horizontally-elongated conductor line directly electrically couples together individual of the channel regions of the pillars of a plurality of the vertical transistors. An upper source/drain region is above the individual channel regions of the pillars, a lower source/drain region is below the individual channel regions of the pillars, and a conductive gate line is operatively aside the individual channel regions of the pillars and that interconnects multiple of the vertical transistors. Methods are disclosed.

## Claims

### Claim 1

An array of vertical transistors, comprising:
spaced pillars individually comprising a channel region of individual vertical transistors;
a horizontally-elongated conductor line directly electrically coupling together individual of the channel regions of the pillars of a plurality of the vertical transistors; and
an upper source/drain region above the individual channel regions of the pillars, a lower source/drain region below the individual channel regions of the pillars, and a conductive gate line operatively aside the individual channel regions of the pillars and that interconnects multiple of the vertical transistors.

### Claim 2 (depends on 1)

The array of claim 1 wherein the conductor line has a top that is lower than a top of the channel region of the transistor-material lines that are on both lateral sides of the conductor line.

### Claim 3 (depends on 1)

The array of claim 1 wherein the conductor line has a top that is elevationally-coincident with a top of the channel region of the transistor-material lines that are on both lateral sides of the conductor line.

### Claim 4 (depends on 1)

The array of claim 1 wherein the conductor line is directly electrically coupled to the channel region of the individual vertical transistors on both lateral sides of the conductor line by conducting material that is directly against and spans between the conductor line and the channel region on both lateral sides of the conductor line, the conducting material is directly against a lateral side of the conductor line.

### Claim 5 (depends on 4)

The array of claim 4 wherein the conducting material where directly against the conductor line is directly against only the lateral side of the conductor line.

### Claim 6 (depends on 1)

The array of claim 1 wherein the conductor line is directly electrically coupled to the channel region of the individual vertical transistors by conducting material that is directly against the conductor line and the channel region, the conducting material is directly against a top of the conductor line.

### Claim 7 (depends on 6)

The array of claim 6 wherein the conducting material where directly against the conductor line is directly against only the top of the conductor line.

### Claim 8 (depends on 1)

The array of claim 1 wherein a continuous line of the transistor material runs horizontally below and from which the pillars project upwardly.

### Claim 9 (depends on 1)

The array of claim 1 wherein the conductor line and the conductive gate line are angled relative one another.

### Claim 10 (depends on 1)

The array of claim 1 wherein the upper source/drain region is in individual of the pillars.

### Claim 11 (depends on 1)

The array of claim 1 wherein the lower source/drain region is in individual of the pillars.

### Claim 12 (depends on 1)

The array of claim 1 wherein the upper and lower source/drain regions are in individual of the pillars.

### Claim 13 (depends on 1)

The array of claim 1 wherein the vertical transistors comprise individual memory cells of a memory array.

### Claim 14

An array of vertical transistors, comprising:
spaced first pillars individually comprising a channel region of individual vertical transistors and an upper source/drain region directly above the channel region;
a conductor line horizontally-elongated in a column direction directly electrically coupling together individual of the channel regions of the first pillars of a plurality of the vertical transistors, the conductor line comprising spaced conductive second pillars projecting upwardly from a continuous line of conductor material of the conductor line;
a lower source/drain region below the individual channel regions of the first pillars; and
a conductive gate line operatively aside the individual channel regions of the first pillars and that interconnects multiple of the vertical transistors in a row direction.

### Claim 15 (depends on 14)

The array of claim 14 wherein the conductor line and the spaced conductive second pillars comprise conductively-doped semiconductive material.

### Claim 16 (depends on 14)

The array of claim 14 wherein the conductor line and the spaced conductive second pillars comprise metal material.

### Claim 17 (depends on 14)

The array of claim 14 wherein the conductor line and the spaced conductive second pillars at least predominately comprise metal material.

### Claim 18 (depends on 14)

The array of claim 14 wherein the spaced conductive second pillars individually have a top that is between a top and a bottom of the channel regions.

### Claim 19 (depends on 14)

The array of claim 14 wherein the spaced conductive second pillars are taller than the conductor lines are vertically thick between the spaced conductive second pillars.

### Claim 20 (depends on 14)

The array of claim 14 wherein individual of the spaced conductive second pillars and individual of the conductor lines have the same maximum lateral thickness relative one another in the column direction.