# US 12,119,267 B2 · Method for manufacturing semiconductor structure

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- Number: US 12,119,267 B2
- Document ID: US12119267B2
- Status: Granted
- Kind: B2
- Application number: 18/151,412
- Filed: 2023-01-06
- Published: 2023-05-18
- Granted: 2024-10-15
- Earliest claimed: 2015-04-24
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chen-Cheng Chou; Shiu-Ko Jangjian; Cheng-Ta Wu
- Web page: https://patentgrep.com/patent/US12119267B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10P 14/6506: {Formation of intermediate materials}
- H10P 14/6512: {by exposure to a gas or vapour}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 95/906: {for altering the shape of semiconductors, e.g. smoothing the surface}
- H10W 10/011: {of isolation regions comprising dielectric materials}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/10: Isolation regions comprising dielectric materials
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 84/834: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes forming patterned masks over a semiconductor substrate; etching the semiconductor substrate using the patterned masks as an etch mask to form semiconductor fins with a trench between the semiconductor fins; performing an annealing process using a hydrogen containing gas to smooth surfaces of the semiconductor fins; after performing the annealing process, selectively forming a first liner on the smoothed surfaces of the semiconductor fins, while leaving surfaces of the patterned masks exposed by the first liner; filling the trench with a dielectric material; and etching back the first liner and the dielectric material to form an isolation structure between the semiconductor fins.

## Claims

### Claim 1

A method, comprising:
forming patterned masks over a semiconductor substrate;
etching the semiconductor substrate using the patterned masks as an etch mask to form semiconductor fins with a trench between the semiconductor fins;
performing an annealing process using a hydrogen containing gas to smooth surfaces of the semiconductor fins;
after performing the annealing process, selectively forming a first liner on the smoothed surfaces of the semiconductor fins, while leaving surfaces of the patterned masks exposed by the first liner;
filling the trench with a dielectric material; and
etching back the first liner and the dielectric material to form an isolation structure between the semiconductor fins.

### Claim 2 (depends on 1)

The method of claim 1, wherein the dielectric material is in contact with the patterned masks.

### Claim 3 (depends on 1)

The method of claim 1, further comprising forming a second liner over the first liner prior to filling the trench with the dielectric material.

### Claim 4 (depends on 3)

The method of claim 3, wherein the first and second liners are formed of silicon oxide.

### Claim 5 (depends on 3)

The method of claim 3, wherein a topmost end of the second liner is below a top surface of one of the patterned masks.

### Claim 6 (depends on 1)

The method of claim 1, wherein a temperature of the annealing process is in a range from about 790 degrees Celsius to about 950 degrees Celsius.

### Claim 7 (depends on 1)

The method of claim 1, wherein the hydrogen containing gas comprises steam (H2O), ammonia (NH3), or combinations thereof.

### Claim 8

A method, comprising:
forming patterned masks over a semiconductor substrate;
etching the semiconductor substrate using the patterned masks as an etch mask to form semiconductor fins with a trench between the semiconductor fins;
forming a first liner on exposed surfaces of the semiconductor fins and the semiconductor substrate;
forming a second liner over the first liner, wherein surfaces of the patterned masks are exposed by the first and second liners;
filling the trench with a dielectric material; and
etching back the first liner, the second liner, and the dielectric material to form an isolation structure between the semiconductor fins.

### Claim 9 (depends on 8)

The method of claim 8, wherein the first and second liners are formed of silicon oxide.

### Claim 10 (depends on 9)

The method of claim 9, wherein the dielectric material is formed of silicon nitride or silicon oxynitride.

### Claim 11 (depends on 8)

The method of claim 8, further comprising:
performing a first annealing process prior to forming the first liner; and
performing a second annealing process after forming the first liner and prior to forming the second liner.

### Claim 12 (depends on 11)

The method of claim 11, wherein the first annealing process is performed using a hydrogen containing gas, and the second annealing process is performed in an oxygen-free environment.

### Claim 13 (depends on 8)

The method of claim 8, wherein the dielectric material is in contact with the patterned masks.

### Claim 14 (depends on 8)

The method of claim 8, further comprising performing a planarization process to the dielectric material prior to etching back the first liner, the second liner, and the dielectric material.

### Claim 15

A method, comprising:
forming patterned masks over a semiconductor substrate;
etching the semiconductor substrate using the patterned masks as an etch mask to form semiconductor fins with a trench between the semiconductor fins;
forming a first liner on exposed surfaces of the semiconductor fins and the semiconductor substrate;
after forming the first liner, performing a first annealing process in an oxygen-free environment;
after performing the first annealing process, forming a second liner over the first liner;
filling the trench with a dielectric material; and
etching back the first liner, the second liner, and the dielectric material to form an isolation structure between the semiconductor fins.

### Claim 16 (depends on 15)

The method of claim 15, further comprising performing a second annealing process prior to forming the first liner.

### Claim 17 (depends on 16)

The method of claim 16, wherein the second annealing process is performed using a hydrogen containing gas.

### Claim 18 (depends on 15)

The method of claim 15, wherein the dielectric material is in contact with the patterned masks.

### Claim 19 (depends on 15)

The method of claim 15, wherein the first liner is formed by oxidizing bottom surfaces and sidewalls of the trench.

### Claim 20 (depends on 15)

The method of claim 15, further comprising performing a planarization process to the dielectric material until top surfaces of the patterned masks are exposed.