# US 12,119,266 B2 · Semiconductor arrangement and method of manufacture

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- Number: US 12,119,266 B2
- Document ID: US12119266B2
- Status: Granted
- Kind: B2
- Application number: 18/142,142
- Filed: 2023-05-02
- Published: 2023-08-24
- Granted: 2024-10-15
- Earliest claimed: 2018-10-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Limited
- Inventors: Kuo-Cheng Ching; Lung-Kun Chu; Mao-Lin Huang; Chung-Wei Hsu
- Web page: https://patentgrep.com/patent/US12119266B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 84/0144: {Manufacturing their gate insulating layers}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/834: {comprising FinFETs}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for forming a semiconductor arrangement comprises forming a first fin in a semiconductor layer. A first gate dielectric layer includes a first high-k material is formed over the first fin. A first sacrificial gate electrode is formed over the first fin. A dielectric layer is formed adjacent the first sacrificial gate electrode and over the first fin. The first sacrificial gate electrode is removed to define a first gate cavity in the dielectric layer. A second gate dielectric layer including a second dielectric material different than the first high-k material is formed over the first gate dielectric layer in the first gate cavity. A first gate electrode is formed in the first gate cavity over the second gate dielectric layer.

## Claims

### Claim 1

A semiconductor arrangement, comprising:
a first fin;
a first gate structure over the first fin, the first gate structure comprising:
a first gate dielectric layer comprising a first high-k dielectric material;
a second gate dielectric layer comprising a second dielectric material different than the first high-k dielectric material over the first gate dielectric layer, wherein the first gate dielectric layer is between a sidewall of the first fin and a sidewall of the second gate dielectric layer; and
a first gate electrode over the second gate dielectric layer; and
a cap layer over the first gate electrode, wherein the first gate structure comprises a sidewall spacer separated from the cap layer by the second gate dielectric layer in a direction parallel to a top surface of the first gate structure.

### Claim 2 (depends on 1)

The semiconductor arrangement of claim 1, wherein:
the sidewall spacer is separated from the first gate electrode by the second gate dielectric layer.

### Claim 3 (depends on 1)

The semiconductor arrangement of claim 1, comprising:
a third gate dielectric layer under the first gate dielectric layer.

### Claim 4 (depends on 3)

The semiconductor arrangement of claim 3, wherein:
the sidewall spacer is in direct contact with the first gate dielectric layer and the third gate dielectric layer.

### Claim 5 (depends on 3)

The semiconductor arrangement of claim 3, wherein the third gate dielectric layer is between the sidewall of the first fin and a sidewall of the first gate dielectric layer.

### Claim 6 (depends on 1)

The semiconductor arrangement of claim 1, wherein the sidewall spacer is separated from the cap layer by the first gate dielectric layer in the direction parallel to the top surface of the first gate structure.

### Claim 7 (depends on 1)

The semiconductor arrangement of claim 1, wherein the sidewall spacer is separated from the first gate electrode by the first gate dielectric layer.

### Claim 8 (depends on 1)

The semiconductor arrangement of claim 1, comprising:
a second fin; and
a second gate structure over the second fin, the second gate structure comprising:
the first gate dielectric layer; and
a second gate electrode in direct contact with the first gate dielectric layer.

### Claim 9 (depends on 1)

The semiconductor arrangement of claim 1, wherein the first gate electrode is separated from the first fin by the first gate dielectric layer and the second gate dielectric layer.

### Claim 10

A semiconductor arrangement, comprising:
a first fin;
a first gate structure over the first fin, the first gate structure comprising:
a first gate dielectric layer;
a second gate dielectric layer over the first gate dielectric layer;
a third gate dielectric layer over the second gate dielectric layer; and
a first gate electrode over the third gate dielectric layer and spaced apart from the second gate dielectric layer by the third gate dielectric layer;
a second fin; and
a second gate structure over the second fin, the second gate structure comprising:
the first gate dielectric layer;
the second gate dielectric layer over the first gate dielectric layer; and
a second gate electrode over the second gate dielectric layer and in direct contact with the second gate dielectric layer.

### Claim 11 (depends on 10)

The semiconductor arrangement of claim 10, wherein:
the first gate structure comprises a sidewall spacer, and
the sidewall spacer is separated from the third gate dielectric layer by the second gate dielectric layer.

### Claim 12 (depends on 11)

The semiconductor arrangement of claim 11, wherein the sidewall spacer is in direct contact with the second gate dielectric layer.

### Claim 13 (depends on 10)

The semiconductor arrangement of claim 10, wherein:
the first gate structure comprises a sidewall spacer, and
the sidewall spacer is in direct contact with the second gate dielectric layer.

### Claim 14 (depends on 10)

The semiconductor arrangement of claim 10, comprising:
a cap layer over the second gate electrode, wherein the second gate structure comprises a sidewall spacer separated from the cap layer by the second gate dielectric layer in a direction parallel to a top surface of the second gate structure.

### Claim 15

A method for forming a semiconductor arrangement, comprising:
forming a first gate electrode;
forming a dielectric layer adjacent the first gate electrode;
removing the first gate electrode to define a first gate cavity in the dielectric layer;
forming a first gate dielectric layer comprising a first high-k dielectric material in the first gate cavity;
forming a second gate dielectric layer comprising a second dielectric material different than the first high-k dielectric material over the first gate dielectric layer in the first gate cavity, wherein a sidewall of the dielectric layer is separated from a second sidewall of the second gate dielectric layer by the first gate dielectric layer;
forming a second gate electrode in the first gate cavity over the second gate dielectric layer; and
recessing the second gate electrode to reduce a height of the second gate electrode such that an uppermost surface of the second gate dielectric layer is above an uppermost surface of the second gate electrode.

### Claim 16 (depends on 15)

The method of claim 15, comprising:
forming a first fin, wherein the first gate dielectric layer is between a sidewall of the first fin and a first sidewall of the second gate dielectric layer.

### Claim 17 (depends on 15)

The method of claim 15, comprising:
forming a third gate dielectric layer, wherein forming the first gate dielectric layer comprises forming the first gate dielectric layer over the third gate dielectric layer.

### Claim 18 (depends on 15)

The method of claim 15, wherein:
recessing the second gate electrode in the first gate cavity defines a recess; and
the method comprises forming a cap layer in the recess over the second gate electrode.

### Claim 19 (depends on 15)

The method of claim 15, comprising:
defining a second gate cavity in the dielectric layer;
forming the first gate dielectric layer in the second gate cavity;
forming the second gate dielectric layer in the second gate cavity;
removing the second gate dielectric layer from the second gate cavity; and
forming a third gate electrode in the second gate cavity over the first gate dielectric layer after removing the second gate dielectric layer from the second gate cavity.

### Claim 20 (depends on 18)

The method of claim 18, comprising:
wherein forming the cap layer comprises forming the cap layer to directly contact a sidewall of the second gate dielectric layer.