# US 12,119,264 B2 · Non-step nanosheet structure for stacked field-effect transistors

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- Number: US 12,119,264 B2
- Document ID: US12119264B2
- Status: Granted
- Kind: B2
- Application number: 17/809,595
- Filed: 2022-06-29
- Published: 2024-01-04
- Granted: 2024-10-15
- Earliest claimed: 2022-06-29
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Shogo Mochizuki; Gen Tsutsui
- Web page: https://patentgrep.com/patent/US12119264B2

## CPC

- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/026: {having laterally-coplanar source and drain regions, a gate at the sides of the bulk channel, and both horizontal and vertical current flow (of LDMOS H10D30/0289)}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 84/0128: {Manufacturing their channels}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Embodiments herein include semiconductor structures that may include a first field-effect transistor (FET) stacked above a second FET in a non-step nanosheet structure, and a bottom contact electrically connected to a first bottom source/drain (S/D) of the second FET through a portion of a first top S/D of the first FET.

## Claims

### Claim 1

A semiconductor structure, comprising:
a first field-effect transistor (FET) stacked above a second FET in a non-step nanosheet structure, wherein the first FET comprises a nanosheet layer at least partially unconnected to the first top S/D; and
a bottom contact electrically connected to a first bottom source/drain (S/D) of the second FET through a portion of a first top S/D of the first FET.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, further comprising a liner surrounding the bottom contact.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, wherein the liner is located directly between the bottom contact and the first FET.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, further comprising a top contact laterally adjacent to the bottom contact.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein the second FET comprises a nanosheet layer completely connected to the first bottom S/D.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein the first FET comprises a top nanosheet layer comprising a first length and width, and the second FET comprises a bottom nanosheet layer comprising a second length and width equal to the first length and width.

### Claim 7

A semiconductor structure, comprising:
a top field-effect transistor (FET), comprising:
a top nanosheet; and
a top source/drain (S/D), wherein the top nanosheet is wider than the top S/D;
a bottom FET, comprising:
a bottom nanosheet; and
a bottom S/D, wherein the bottom nanosheet has a same width as the top nanosheet, and the bottom S/D is wider than the top S/D; and
a bottom contact electrically connected to the bottom S/D through a portion of a first top S/D of the first FET.

### Claim 8 (depends on 7)

The semiconductor structure of claim 7, further comprising a top contact laterally adjacent to the bottom contact.

### Claim 9 (depends on 7)

The semiconductor structure of claim 7, further comprising a liner surrounding the bottom contact.

### Claim 10 (depends on 9)

The semiconductor structure of claim 9, wherein the liner is located between the bottom contact and the top nanosheet.

### Claim 11 (depends on 9)

The semiconductor structure of claim 9, wherein the liner is located between the bottom contact and the top contact.

### Claim 12 (depends on 9)

The semiconductor structure of claim 9, wherein the liner is located between the bottom contact and the top S/D.

### Claim 13 (depends on 7)

The semiconductor structure of claim 7, further comprising an isolation layer between the top FET and the bottom FET.