# US 12,119,263 B2 · Methods and apparatus for an improved integrated circuit package

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- Number: US 12,119,263 B2
- Document ID: US12119263B2
- Status: Granted
- Kind: B2
- Application number: 17/317,845
- Filed: 2021-05-11
- Published: 2021-08-26
- Granted: 2024-10-15
- Earliest claimed: 2017-03-19
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Makoto Shibuya
- Web page: https://patentgrep.com/patent/US12119263B2

## CPC

- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10W 70/048: {Mechanical treatments, e.g. punching, cutting, deforming or cold welding}
- H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)}
- H10W 70/457: {of metallic layers on leadframes}
- H10W 72/50: Bond wires
- H10W 72/90: Bond pads, in general
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 72/0198: {batch processes}
- H10W 72/07254: {changes in dispositions}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/321: {Structures or relative sizes of die-attach connectors}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/014: {using batch processing}
- H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In a described example, an integrated circuit (IC) package includes an IC die disposed on a die attach pad; a plurality of leads electrically connected to terminals on the IC die, the leads including a base metal; and molding compound material encapsulating portions of the IC die, the die attach pads, and the plurality of leads; the plurality of leads having a solder joint reinforcement tab. The solder joint reinforcement tabs include a first side, a second side opposite to the first side, a third side, a fourth side opposite to and in parallel to the third side, a fifth side forming an end portion of the solder joint reinforcement tab, the solder joint reinforcement tabs including a solderable metal layer on the second, third and fourth sides and on portions of the fifth side.

## Claims

### Claim 1

A method for forming an integrated circuit (IC) package, comprising:
providing a lead frame strip of lead frame material having a first side and a second side opposite the first side with integrated circuit (IC) dies attached to the first side of the lead frame strip and covered in molding compound material, the integrated circuit dies spaced apart by saw street regions;
from the first side of the lead frame strip, in a saw street between ones of the IC dies, making a first cut of a first width through the molding compound and into the first side of the lead frame strip, leaving a band of the lead frame material and molding compound material in the saw street between adjacent IC dies;
making a second cut of a second width that is less than the first width through the band of the lead frame material and molding compound material in the saw street to form a ledge of saw street material comprised of a plurality of solder joint reinforcement tabs separated by molding compound material; and
removing the molding compound material from between the solder joint reinforcement tabs such that the solder joint reinforcement tabs extend from a periphery of the IC package.

### Claim 2 (depends on 1)

The method of claim 1, in which the band of the lead frame material and molding compound material has a thickness in a range of 30 μm to 50 μm.

### Claim 3 (depends on 1)

The method of claim 1, in which the solder joint reinforcement tabs have a length extending longitudinally in a first direction from a periphery of the IC package in a range of about 30 μm to 70 μm, and the solder joint reinforcement tabs have a first side oriented in the first direction, a second side opposite to and in parallel with the first side, a third side oriented in a second direction perpendicular to the first side, a fourth side opposite to and in parallel with the third side, and a fifth side forming an end portion of the solder joint reinforcement tab, the second side, third side and the fourth side being covered by a solderable metal layer, and the first side and the fifth side being partially covered by the solderable metal layer.

### Claim 4 (depends on 3)

The method of claim 3, further including bending the solder joint reinforcement tabs into a vertical orientation against a side of the molding compound of the packaged integrated circuit.

### Claim 5 (depends on 1)

The method of claim 1, in which the packaged integrated circuit is a Quad Flat No Lead (QFN) packaged integrated circuit.

### Claim 6 (depends on 1)

The method of claim 1, in which the solder joint reinforcement tab has a thickness in a range of about 30 μm to 50 μm.

### Claim 7 (depends on 1)

The method of claim 1, in which the solder joint reinforcement tab has a length extending longitudinally in the first direction from a periphery of the IC package of about 30 μm to 70 μm.

### Claim 8 (depends on 1)

The method of claim 1, in which the solder joint reinforcement tab projects horizontally from a base of the IC package.

### Claim 9 (depends on 1)

The method of claim 1, in which the solder joint reinforcement tab extends alongside a vertical sidewall of the IC package.

### Claim 10

A method for forming an integrated circuit (IC) package, comprising:
attaching an IC die to a die mount pad and electrically connecting the IC die to a lead;
covering the IC die and portions of the lead using a molding compound; and
sawing a side of the molding compound to form a side of the IC package, the side of the IC package including a solder joint reinforcement tab projecting from the side of the IC package, the solder joint reinforcement tab has a first side oriented in the first direction, a second side opposite to and in parallel with the first side, a third side oriented in a second direction perpendicular to the first side, a fourth side opposite to and in parallel with the third side, and a fifth side forming an end portion of the solder joint reinforcement tab, the second side, third side and the fourth side being covered by a solderable metal layer, and the first side and the fifth side being partially covered by the solderable metal layer.

### Claim 11 (depends on 10)

The method of claim 10, in which the IC package is one selected from a Small Outline No-Lead (SON) package and a Quad Flat No-Lead (QFN) package.

### Claim 12 (depends on 10)

The method of claim 10, in which the first side and the fifth side includes a base metal of the lead visible.

### Claim 13 (depends on 10)

The method of claim 10, in which the solderable metal layer includes at least one selected from nickel, gold, palladium, and alloys thereof.

### Claim 14 (depends on 10)

The method of claim 10, in which the base metal includes copper or a copper alloy.

### Claim 15 (depends on 10)

The method of claim 10, in which the solder joint reinforcement tab has a thickness in a range of about 30 μm to 50 μm.

### Claim 16 (depends on 10)

The method of claim 10, in which sawing a side of the molding compound includes sawing from a top of the side and then sawing from a bottom of the side using blades of different thickness.