# US 12,119,259 B2 · Transistor gate contacts and methods of forming the same

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- Number: US 12,119,259 B2
- Document ID: US12119259B2
- Status: Granted
- Kind: B2
- Application number: 17/325,477
- Filed: 2021-05-20
- Published: 2022-09-29
- Granted: 2024-10-15
- Earliest claimed: 2021-03-26
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Kai-Hsuan Lee; Sai-Hooi Yeong; Chi On Chui
- Web page: https://patentgrep.com/patent/US12119259B2

## CPC

- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10W 20/076: {in via holes or trenches}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10D 64/679: {comprising air gaps}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/0698: {Local interconnections}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/46: comprising air gaps
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 84/0158: {the components including FinFETs}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/83125: {the IGFETs characterised by having shared source or drain regions}
- H10D 84/8316: {the IGFETs characterised by having gate sidewall spacers specially adapted for integration}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In an embodiment, a device includes: a source/drain region adjoining a channel region of a substrate; a contact etch stop layer on the source/drain region; a first source/drain contact extending through the contact etch stop layer, the first source/drain contact connected to the source/drain region; a gate structure on the channel region; a gate contact connected to the gate structure; and a contact spacer around the gate contact, where the contact spacer, the gate structure, the contact etch stop layer, and the substrate collectively define a void between the gate structure and the first source/drain contact.

## Claims

### Claim 1

A method comprising:
etching a first contact opening through a gate mask to expose a gate structure and a gate spacer, the gate spacer disposed along a sidewall of the gate structure and along a sidewall of the gate mask;
removing the gate spacer to extend the first contact opening along the sidewall of the gate structure to form a first extended contact opening;
depositing a spacer layer in an upper portion of the first extended contact opening over the gate structure, the spacer layer sealing a lower portion of the first extended contact opening along the sidewall of the gate structure to form a void from the lower portion of the first extended contact opening; and
forming a gate contact in the upper portion of the first extended contact opening, the gate contact connected to the gate structure, the spacer layer disposed around the gate contact.

### Claim 2 (depends on 1)

The method of claim 1 further comprising:
growing a source/drain region adjoining a channel region, the gate structure disposed over the channel region;
depositing a first inter-layer dielectric over the source/drain region;
etching a source/drain contact opening through the first inter-layer dielectric to expose the source/drain region, the gate mask covering the gate structure while etching the source/drain contact opening; and
forming a lower source/drain contact in the source/drain contact opening, the lower source/drain contact connected to the source/drain region.

### Claim 3 (depends on 2)

The method of claim 2, wherein top surfaces of the lower source/drain contact, the gate mask, and the gate spacer are coplanar.

### Claim 4 (depends on 2)

The method of claim 2 further comprising:
forming a contact mask over the lower source/drain contact, top surfaces of the contact mask, the gate mask, and the gate spacer being coplanar.

### Claim 5 (depends on 2)

The method of claim 2 further comprising:
depositing a second inter-layer dielectric over the lower source/drain contact, the gate mask, and the gate spacer, wherein the first contact opening is also etched through the second inter-layer dielectric; and
before removing the gate spacer, widening the first contact opening to expose the lower source/drain contact, the spacer layer further deposited over the lower source/drain contact.

### Claim 6 (depends on 1)

The method of claim 1, wherein the sidewall of the gate structure is free of the spacer layer.

### Claim 7 (depends on 1)

The method of claim 1, wherein the sidewall of the gate structure contacts the spacer layer.

### Claim 8 (depends on 1)

The method of claim 1, wherein etching the first contact opening through the gate mask comprises performing an anisotropic etching process, and removing the gate spacer comprises performing an isotropic etching process.

### Claim 9 (depends on 8)

The method of claim 8, wherein the gate mask comprises silicon nitride, and the anisotropic etching process is a dry etch performed with carbon tetrafluoride.

### Claim 10 (depends on 8)

The method of claim 8, wherein the gate spacer comprises silicon nitride, and the isotropic etching process is a wet etch performed with phosphoric acid.

### Claim 11 (depends on 1)

The method of claim 1 further comprising:
growing a source/drain region adjoining a channel region, the gate structure disposed over the channel region;
depositing a first inter-layer dielectric over the source/drain region;
etching a source/drain contact opening through the first inter-layer dielectric to expose the source/drain region, the gate mask covering the gate structure while etching the source/drain contact opening;
forming a lower source/drain contact in the source/drain contact opening, the lower source/drain contact connected to the source/drain region;
forming a contact mask over the lower source/drain contact;
depositing a second inter-layer dielectric over the contact mask, the gate mask, and the gate spacer, wherein the first contact opening is also etched through the second inter-layer dielectric;
before removing the gate spacer, widening the first contact opening to expose the contact mask; and
extending the first contact opening through the contact mask to expose the lower source/drain contact, the spacer layer further deposited over the lower source/drain contact.

### Claim 12

A method comprising:
etching a first contact opening through an etch stop layer to expose a gate structure and a gate spacer, the gate spacer disposed along a sidewall of the gate structure;
removing the gate spacer to extend the first contact opening along the sidewall of the gate structure to form an extended contact opening;
forming a contact spacer in an upper portion of the extended contact opening over the gate structure, the contact spacer sealing a lower portion of the extended contact opening along the sidewall of the gate structure to form a void from the lower portion of the extended contact opening; and
forming a gate contact in the upper portion of the extended contact opening, the gate contact connected to the gate structure, the contact spacer disposed around the gate contact.

### Claim 13 (depends on 12)

The method of claim 12, wherein forming the contact spacer comprises:
depositing a spacer layer in the upper portion of the extended contact opening; and
patterning the spacer layer to remove a horizontal portion of the spacer layer over the gate structure.

### Claim 14 (depends on 12)

The method of claim 12, wherein the contact spacer extends through the etch stop layer.

### Claim 15 (depends on 12)

The method of claim 12, wherein the sidewall of the gate structure is free of the contact spacer.

### Claim 16 (depends on 12)

The method of claim 12, wherein the sidewall of the gate structure contacts the contact spacer.

### Claim 17 (depends on 12)

The method of claim 12, wherein etching the first contact opening through the etch stop layer comprises performing an anisotropic etching process, and removing the gate spacer comprises performing an isotropic etching process.

### Claim 18 (depends on 12)

The method of claim 12, further comprising:
expanding the first contact opening to expose a source/drain contact, the source/drain contact connected to a source/drain region, the source/drain region adjoining a channel region, the gate structure disposed over the channel region.

### Claim 19

A method comprising:
etching a contact opening through an etch stop layer to expose a gate structure and a gate spacer, the gate spacer disposed along a sidewall of the gate structure;
expanding the contact opening to expose a source/drain contact, the source/drain contact connected to a source/drain region, the gate spacer disposed along a sidewall of the source/drain region;
removing the gate spacer to extend the contact opening along the sidewall of the gate structure and along the sidewall of the source/drain region to form an extended contact opening;
forming a contact spacer in an upper portion of the extended contact opening over the gate structure, the contact spacer sealing a lower portion of the extended contact opening along the sidewall of the gate structure and along the sidewall of the source/drain region; and
forming a gate contact in the upper portion of the extended contact opening, the gate contact connected to the gate structure and to the source/drain contact, a portion of the contact spacer disposed beneath the gate contact.

### Claim 20 (depends on 19)

The method of claim 19, wherein etching the contact opening through the etch stop layer comprises performing an anisotropic etching process, and removing the gate spacer comprises performing an isotropic etching process.