# US 12,119,238 B2 · Semiconductor bonding structures and methods

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- Number: US 12,119,238 B2
- Document ID: US12119238B2
- Status: Granted
- Kind: B2
- Application number: 16/588,588
- Filed: 2019-09-30
- Published: 2020-01-30
- Granted: 2024-10-15
- Earliest claimed: 2013-10-02
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Meng-Tse Chen; Hsiu-Jen Lin; Wei-Hung Lin; Kuei-Wei Huang; Ming-Da Cheng; Chung-Shi Liu
- Web page: https://patentgrep.com/patent/US12119238B2

## CPC

- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/00: Package configurations
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01236: {in solid form, e.g. by using a powder or by laminating a foil}
- H10W 72/01238: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01257: {by reflowing}
- H10W 72/0198: {batch processes}
- H10W 72/07141: {Means for applying energy, e.g. ovens or lasers}
- H10W 72/072: {of bump connectors}
- H10W 72/07232: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07235: {Applying EM radiation, e.g. induction heating or using a laser}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/07252: {changes in structures or sizes}
- H10W 72/07254: {changes in dispositions}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07338: {hardening the adhesive by curing, e.g. thermosetting}
- H10W 72/07352: {changes in structures or sizes}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/257: {Multiple bump connectors having different materials}
- H10W 72/321: {Structures or relative sizes of die-attach connectors}
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/331: {Shapes of die-attach connectors}
- H10W 72/354: {comprising polymers}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A system and method for applying an underfill is provided. An embodiment comprises applying an underfill to a substrate and patterning the underfill. Once patterned other semiconductor devices, such as semiconductor dies or semiconductor packages may then be attached to the substrate through the underfill, with electrical connections from the other semiconductor devices extending into the pattern of the underfill.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
removing a first portion of an underfill material to form a first opening exposing a first portion of a substrate, the first opening having a first width and a first depth;
removing a second portion of the underfill material to form a second opening exposing a second portion of the substrate, the second opening having a second width and a second depth, the second width being different from the first width, the second depth being the same as the first depth, wherein the removing the first portion of the underfill material and the removing the second portion of the underfill material are performed simultaneously, and wherein after removing the first portion of the underfill material and the second portion of the underfill material, the remaining portion of the underfill material has a planar top surface;
after the removing the first portion of the underfill material, placing a first external connector into physical contact with the first portion of the substrate, the first external connector having a third width; and
after the removing the second portion of the underfill material, bonding a first package to the substrate by placing a second external connector into physical contact with the second portion of the substrate, the second external connector having a fourth width larger than the third width, wherein a continuous flat top surface of the underfill material between the first external connector and the second external connector is exposed while bonding the first package by placing the second external connector.

### Claim 2 (depends on 1)

The method of claim 1, wherein the second width is between about 50 μm and about 300 μm.

### Claim 3 (depends on 1)

The method of claim 1, wherein the second external connector is a solder ball connected to a first package.

### Claim 4 (depends on 3)

The method of claim 3, wherein the first external connector is a solder ball connected to a first semiconductor die.

### Claim 5 (depends on 3)

The method of claim 3, wherein the first external connector is a copper pillar connected to a first semiconductor die.

### Claim 6

A method of manufacturing a semiconductor device, the method comprising:
applying an underfill material to a substrate;
patterning the underfill material to form a first opening through the underfill material and a second opening through the underfill material, wherein the patterning the underfill to form the first opening and the second opening are performed simultaneously, wherein the first opening has a first width, the second opening has a second width, and the first width is different from the second width, wherein the first opening has a first depth, the second opening has a second depth, and the second depth is the same as the first depth, wherein the patterning the underfill material removes material of the underfill material to expose the substrate; and
after the patterning the underfill material, bonding a first semiconductor die to the substrate through the first opening and bonding a first package to the substrate through the second opening, wherein bonding the first package to the substrate comprises forming a first external connector in physical contact with the substrate and with the first package, wherein the first external connector comprises a first material extending from a bottom surface of the second opening to a bottom surface of the first package, wherein a portion of a continuous sidewall of the first external connector is free of contact with the underfill material, and wherein a top surface of the underfill material adjacent the second opening is exposed while bonding the first package to the substrate.

### Claim 7 (depends on 6)

The method of claim 6, further comprising forming second external connectors to the substrate, wherein the second external connectors are located on an opposite side of the substrate from the first semiconductor die.

### Claim 8 (depends on 6)

The method of claim 6, wherein the first width is between about 10 μm and about 100 μm.

### Claim 9 (depends on 8)

The method of claim 8, wherein the second width is between about 50 μm and about 400 μm.

### Claim 10 (depends on 6)

The method of claim 6, further comprising partially curing the underfill material prior to the patterning the underfill material.

### Claim 11 (depends on 10)

The method of claim 10, further comprising curing the underfill material after the bonding the first semiconductor die.

### Claim 12

A method of manufacturing a semiconductor device, the method comprising:
laminating an underfill material onto a substrate, wherein after the laminating the underfill material the entirety of the underfill material has an uppermost planar surface facing away from the substrate;
removing a first portion of the underfill material to form a first opening exposing a first portion of a substrate, the first opening having a first width and a first depth;
after the removing the first portion of the underfill material, bonding a first semiconductor die to the substrate with a first external connector;
removing a second portion of the underfill material to form a second opening exposing a second portion of a substrate, the second opening having a second width and a second depth;
the second width being different from the first width, the second depth being the same as the first depth, wherein removing the first portion of the underfill material and removing the second portion of the underfill material are performed simultaneously; and
after the laminating the underfill material, bonding a first package to the substrate with a second external connector, the first external connector having a third width, the second external connector having a fourth width larger than the third width, wherein the second external connector physically contacts a top surface of the substrate and a bottom surface of the first package, wherein the second external connector comprises a first material extending from the top surface of the substrate to the bottom surface of the first package, wherein a sidewall of the second external connector is partially exposed from the underfill material, and wherein the uppermost planar surface of the underfill material is exposed while bonding the first package to the substrate.

### Claim 13 (depends on 12)

The method of claim 12, further comprising partially curing the underfill material prior to the bonding a first semiconductor die.

### Claim 14 (depends on 13)

The method of claim 13, further comprising fully curing the underfill material after the bonding the first semiconductor die.

### Claim 15 (depends on 12)

The method of claim 12, wherein after removing the first portion of the underfill material and removing the second portion of the underfill material, a first portion of the uppermost planar surface of the underfill material abuts a sidewall of the first opening and a sidewall of the second opening.

### Claim 16 (depends on 15)

The method of claim 15, wherein after bonding the first package to the substrate, a cavity extends continuously from the first portion of the uppermost planar surface of the underfill material to the bottom surface of the first package.

### Claim 17 (depends on 12)

The method of claim 12, wherein the bonding the first semiconductor die comprises placing the first external connector within the first opening and wherein the bonding the first package comprises placing the second external connector within the second opening.

### Claim 18 (depends on 17)

The method of claim 17, wherein the first external connector comprises a copper pillar and the second external connector comprises solder.

### Claim 19 (depends on 17)

The method of claim 17, wherein the first opening has a first width of between about 10 μm and about 100 μm.

### Claim 20 (depends on 19)

The method of claim 19, wherein the second opening has a second width of between about 50 μm and about 400 μm.