# US 12,119,237 B2 · Semiconductor device package having metal thermal interface material > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,119,237 B2 - Document ID: US12119237B2 - Status: Granted - Kind: B2 - Application number: 18/349,292 - Filed: 2023-07-10 - Published: 2023-12-21 - Granted: 2024-10-15 - Earliest claimed: 2021-05-07 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Chien-Li Kuo; Chin-Fu Kao; Chen-Shien Chen - Web page: https://patentgrep.com/patent/US12119237B2 ## CPC - H10W 40/037: {Assembling together parts thereof} - H10W 40/70: Fillings or auxiliary members in containers or in encapsulations for thermal protection or control - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/611: {for connecting multiple chips together} - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/685: comprising multiple insulating layers - H10W 74/016: {using moulds} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation} - H10W 90/00: Package configurations - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 95/00: Packaging processes not covered by the other groups of this subclass - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/6528: {of the portions that connect to chips, wafers or package parts} - H10W 72/0113: {Apparatus for manufacturing die-attach connectors} - H10W 72/013: {of die-attach connectors} - H10W 72/0711: {Apparatus therefor} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/30: Die-attach connectors - H10W 72/877: {Bump connectors and die-attach connectors} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/01: Manufacture or treatment - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 76/17: characterised by their materials - H10W 90/288: {characterised by arrangements for thermal management of the stacked chips} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device package is provided, including a package substrate, a semiconductor device, a metal lid, and a metal thermal interface material (TIM). The package substrate has a first surface. The semiconductor device is disposed over the first surface of the package substrate. The metal lid is disposed over the semiconductor device and the package substrate. The metal TIM is interposed between the metal lid and the top surface of the semiconductor device for bonding the metal lid and the semiconductor device. A shape of the lateral sidewall of the metal TIM in a longitudinal section is concave arc, and the outermost point of the lateral sidewall is within the boundary of the semiconductor device. ## Claims ### Claim 1 A semiconductor device package, comprising: a package substrate having a first surface; a semiconductor device disposed over the first surface of the package substrate; a metal lid disposed over the semiconductor device and the package substrate; and a metal thermal interface material (TIM) interposed between the metal lid and a top surface of the semiconductor device for bonding the metal lid and the semiconductor device, wherein a shape of a lateral sidewall of the metal TIM in a longitudinal section is concave arc, and an outermost point of the lateral sidewall is within a boundary of the semiconductor device. ### Claim 2 (depends on 1) The semiconductor device package as claimed in claim 1, wherein the lateral sidewall of the metal TIM comprises two end points and an intermediate point between the two end points, wherein the two end points are connected to the metal lid and the semiconductor device, respectively, and closer to the boundary of the semiconductor device than the intermediate point in a lateral direction. ### Claim 3 (depends on 2) The semiconductor device package as claimed in claim 2, wherein the two end points of the lateral sidewall of the metal TIM are aligned with the boundary of the semiconductor device. ### Claim 4 (depends on 2) The semiconductor device package as claimed in claim 2, wherein the two end points of the lateral sidewall of the metal TIM are offset from the boundary of the semiconductor device toward a center of the top surface of the semiconductor device. ### Claim 5 (depends on 1) The semiconductor device package as claimed in claim 1, wherein the metal TIM is a solder-based TIM. ### Claim 6 (depends on 1) The semiconductor device package as claimed in claim 1, wherein the metal lid comprises a cover portion above the semiconductor device, and a ring portion extending from the cover portion toward the first surface of the package substrate and surrounding the semiconductor device, and wherein a gap is formed between a bottom surface of the ring portion and the first surface of the package substrate. ### Claim 7 (depends on 1) The semiconductor device package as claimed in claim 1, wherein the metal lid comprises a cover portion above the semiconductor device, and a ring portion extending from the cover portion toward the first surface of the package substrate and surrounding the semiconductor device, and wherein the semiconductor device package further comprises an adhesive layer arranged between a bottom surface of the ring portion and the first surface of the package substrate. ### Claim 8 (depends on 1) The semiconductor device package as claimed in claim 1, wherein when viewed in a horizontal direction parallel to the first surface of the package substrate, the lateral sidewall of the metal TIM close to the boundary of the semiconductor device is in a concave arc shape. ### Claim 9 A semiconductor device package, comprising: a package substrate having a first surface; a semiconductor device disposed over the first surface of the package substrate; a metal lid disposed over the semiconductor device and the package substrate; and a metal thermal interface material (TIM) interposed between the metal lid and a top surface of the semiconductor device for bonding the metal lid and the semiconductor device, wherein an outermost point of the lateral sidewall is within a boundary of the semiconductor device, and wherein there is a gap between a bottom surface of the metal lid and the first surface of the package substrate to make the metal lid separate from the package substrate, wherein the gap extends from an inner wall of the metal lid to an outer wall of the metal lid, and no adhesive is provided in the gap. ### Claim 10 (depends on 9) The semiconductor device package as claimed in claim 9, wherein the metal lid comprises a cover portion above the semiconductor device, and a ring portion extending from the cover portion toward the first surface of the package substrate and surrounding the semiconductor device, wherein the bottom surface of the metal lid is a bottom surface of the ring portion. ### Claim 11 (depends on 9) The semiconductor device package as claimed in claim 9, wherein the outermost point of the lateral sidewall of the molten metal TIM is aligned with the boundary of the semiconductor device in a lateral direction. ### Claim 12 (depends on 11) The semiconductor device package as claimed in claim 11, wherein a shape of the lateral sidewall of the molten metal TIM in a longitudinal section is a concave arc. ### Claim 13 (depends on 11) The semiconductor device package as claimed in claim 11, wherein a shape of the lateral sidewall of the molten metal TIM in a longitudinal section is straight. ### Claim 14 (depends on 9) The semiconductor device package as claimed in claim 9, wherein the outermost point of the lateral sidewall of the molten metal TIM is closer to a center of the top surface of the semiconductor device than the boundary of the semiconductor device in a lateral direction. ### Claim 15 (depends on 14) The semiconductor device package as claimed in claim 14, wherein a shape of the lateral sidewall of the molten metal TIM in a longitudinal section is a concave arc. ### Claim 16 (depends on 14) The semiconductor device package as claimed in claim 14, wherein a shape of the lateral sidewall of the molten metal TIM in a longitudinal section is straight. ### Claim 17 A semiconductor device package, comprising: a package substrate having a first surface; a semiconductor device disposed over the first surface of the package substrate; a metal lid disposed over the semiconductor device and the package substrate; and a solder-based thermal interface material (TIM) interposed between the metal lid and a top surface of the semiconductor device for bonding the metal lid and the semiconductor device, wherein a shape of a lateral sidewall of the solder-based TIM in a longitudinal section is concave arc. ### Claim 18 (depends on 17) The semiconductor device package as claimed in claim 17, wherein the lateral sidewall of the solder-based TIM comprises two end points and an intermediate point between the two end points, wherein the two end points are connected to the metal lid and the semiconductor device, respectively, and closer to a boundary of the semiconductor device than the intermediate point in a lateral direction, and wherein a distance between the intermediate point of the lateral sidewall of the solder-based TIM and an inner wall of a ring portion of the metal lid in the lateral direction is greater than a distance between the boundary of the semiconductor device and the inner wall of the ring portion of the metal lid in the lateral direction. ### Claim 19 (depends on 17) The semiconductor device package as claimed in claim 17, further comprising a buffer layer formed between the top surface of the semiconductor device and the solder-based TIM. ### Claim 20 (depends on 17) The semiconductor device package as claimed in claim 17, further comprising an electronic component mounted on the first surface of the package substrate.