# US 12,119,234 B2 · Semiconductor structure and method for manufacturing same

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- Number: US 12,119,234 B2
- Document ID: US12119234B2
- Status: Granted
- Kind: B2
- Application number: 17/649,064
- Filed: 2022-01-26
- Published: 2022-05-19
- Granted: 2024-10-15
- Earliest claimed: 2020-11-16
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Ping-Heng Wu
- Web page: https://patentgrep.com/patent/US12119234B2

## CPC

- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W 20/01: {Manufacture or treatment}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0238: {comprising etching via holes through pads or through electrodes}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/0249: {wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/2125: {Top-view shapes}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/611: {for connecting multiple chips together}
- H10W 90/00: Package configurations
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure includes: a base; a conductive column, which is at least located in the base; an electric connection layer, which is connected to an end part of the conductive column. The end part, towards the electric connection layer, of the conductive column has a first protruding part and at least one groove defined by the first protruding part, the electric connection layer has a second protruding part at a position corresponding to the groove, and the second protruding part is embedded in the groove.

## Claims

### Claim 1

A method for manufacturing a semiconductor structure, comprising:
providing a base, the base comprising a conductive column region;
forming a first through hole in the base of the conductive column region, a bottom of the first through hole being provided with at least one first protruding structure;
filling the first through hole to form a conductive column, the conductive column being provided with a groove at a first position corresponding to the first protruding structure, and the conductive column being provided with a first protruding part defining the groove;
etching the base close to the first protruding structure to expose a bottom of the groove; and
forming an electric connection layer filling up the groove, the electric connection layer being provided with a second protruding part at a second position corresponding to the groove;
the method further comprising: before forming the first through hole, forming at least one initial isolation structure in the base, wherein the initial isolation structure is at least located in partial conductive column region; and the forming the first through hole comprises:
removing the initial isolation structure located in the conductive column region until the base right below the initial isolation structure is exposed; and
etching the base located in the conductive column region to form the first through hole.

### Claim 2 (depends on 1)

The method for manufacturing a semiconductor structure of claim 1, wherein each initial isolation structure extends into the base adjacent to the conductive column region; after forming the first through hole, a remaining initial isolation structure located in the base adjacent to the conductive column region is used as an isolation structure, and partial side wall of the first through hole formed exposes the side surface of the isolation structure.

### Claim 3 (depends on 1)

The method for manufacturing a semiconductor structure of claim 1, wherein the base comprises a first dielectric layer and a substrate that are successively stacked, and the initial isolation structure is located in the substrate; before removing the initial isolation structure located in the conductive column region, the first dielectric layer corresponding to the conductive column region is etched to expose both the initial isolation structure and the substrate located in the conductive column region.

### Claim 4 (depends on 1)

The method for manufacturing a semiconductor structure of claim 1, wherein the base comprises a first dielectric layer and a substrate that are successively stacked, and an initial isolation structure is provided in the substrate; after etching the base closing to the first protruding structure and before forming the electric connection layer filling up the groove, the method further comprises: forming a third dielectric layer on a side, away from the initial isolation structure, of the substrate, the third dielectric layer exposing the groove, and the third dielectric layer being used as the second dielectric layer.

### Claim 5 (depends on 1)

The method for manufacturing a semiconductor structure of claim 1, wherein the base comprises a first dielectric layer and a substrate that are successively stacked, and an initial isolation structure is provided in the substrate; after etching the base closing to the first protruding structure, the forming the electric connection layer filling up the groove further comprises: forming a fourth dielectric layer on a side, away from the initial isolation structure, of the substrate, the conductive column being located in the fourth dielectric layer; etching the fourth dielectric layer to form a second through hole, the second through hole exposing the groove; filling the second through hole to form the electric connection layer, a remaining fourth dielectric layer that is not etched being used as the second dielectric layer.