# US 12,119,231 B2 · Semiconductor device and method

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- Number: US 12,119,231 B2
- Document ID: US12119231B2
- Status: Granted
- Kind: B2
- Application number: 17/874,694
- Filed: 2022-07-27
- Published: 2022-11-17
- Granted: 2024-10-15
- Earliest claimed: 2020-06-11
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yu-Lien Huang; Guan-Ren Wang; Ching-Feng Fu
- Web page: https://patentgrep.com/patent/US12119231B2

## CPC

- H10P 50/644: {Anisotropic liquid etching (H10P50/61 takes precedence)}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/01125: {the silicides being formed by chemical reaction with the semiconductor after the contact hole formation}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10W 20/0698: {Local interconnections}
- H10W 20/074: {of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/047: {by introducing additional elements therein}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In an embodiment, a structure includes: a contact etch stop layer (CESL) over a substrate; a fin extending through the CESL; an epitaxial source/drain region in the fin, the epitaxial source/drain region extending through the CESL; a silicide contacting upper facets of the epitaxial source/drain region; a source/drain contact contacting the silicide, lower facets of the epitaxial source/drain region, and a first surface of the CESL; and an inter-layer dielectric (ILD) layer surrounding the source/drain contact, the ILD layer contacting the first surface of the CESL.

## Claims

### Claim 1

A device comprising:
an isolation region on a substrate;
a dielectric layer on the isolation region, the dielectric layer comprising a different dielectric material than the isolation region;
a first semiconductor fin extending above the dielectric layer;
a source/drain region in the first semiconductor fin, the source/drain region having upper facets and lower facets, the upper facets and the lower facets raised beyond sidewalls of the first semiconductor fin;
an inter-layer dielectric on the source/drain region and the dielectric layer;
a source/drain contact extending through the inter-layer dielectric, the source/drain contact physically contacting the lower facets of the source/drain region;
a metal-semiconductor alloy region between the source/drain contact and the upper facets of the source/drain region; and
a gate structure above the dielectric layer.

### Claim 2 (depends on 1)

The device of claim 1 further comprising:
a gate structure on the dielectric layer and the sidewalls of the first semiconductor fin.

### Claim 3 (depends on 1)

The device of claim 1 further comprising:
a second semiconductor fin extending above the dielectric layer, the source/drain region disposed in the second semiconductor fin.

### Claim 4 (depends on 3)

The device of claim 3 further comprising:
a void between the first semiconductor fin and the second semiconductor fin, the void disposed beneath the source/drain region.

### Claim 5 (depends on 1)

The device of claim 1, wherein the source/drain region extends through the dielectric layer.

### Claim 6 (depends on 1)

The device of claim 1, the lower facets of the source/drain region are free from the metal-semiconductor alloy region.

### Claim 7

A device comprising:
an isolation region on a substrate;
a contact etch stop layer on the isolation region;
a first fin extending through the contact etch stop layer and the isolation region;
a second fin extending through the contact etch stop layer and the isolation region;
an epitaxial source/drain region in the first fin and the second fin, the epitaxial source/drain region disposed over a first portion of the contact etch stop layer, the first portion of the contact etch stop layer laterally disposed between the first fin and the second fin;
an inter-layer dielectric on the epitaxial source/drain region and a second portion of the contact etch stop layer; and
a source/drain contact extending through the inter-layer dielectric, the source/drain contact contacting the second portion of the contact etch stop layer and lower facets of the epitaxial source/drain region.

### Claim 8 (depends on 7)

The device of claim 7 further comprising:
a metal-semiconductor alloy region on upper facets of the epitaxial source/drain region, the source/drain contact contacting the metal-semiconductor alloy region.

### Claim 9 (depends on 7)

The device of claim 7 further comprising:
a void beneath the epitaxial source/drain region, the void exposing the first portion of the contact etch stop layer and a subset of the lower facets of the epitaxial source/drain region.

### Claim 10 (depends on 7)

The device of claim 7, wherein interfaces of the contact etch stop layer and the source/drain contact are parallel to a major surface of the substrate.

### Claim 11 (depends on 7)

The device of claim 7, wherein the lower facets of the epitaxial source/drain region are free from the contact etch stop layer.

### Claim 12 (depends on 7)

The device of claim 7, wherein the lower facets of the epitaxial source/drain region are free from the inter-layer dielectric.

### Claim 13 (depends on 7)

The device of claim 7, wherein the inter-layer dielectric comprises silicon oxide and the contact etch stop layer comprises silicon nitride.

### Claim 14 (depends on 7)

The device of claim 7, wherein the first fin and the second fin are each epitaxial structures disposed on the substrate.

### Claim 15 (depends on 7)

The device of claim 7, further comprising:
a gate structure on the first fin and the second fin, the gate structure contacting the first portion and the second portion of the contact etch stop layer.

### Claim 16

A device comprising:
a contact etch stop layer over a substrate;
a fin extending through the contact etch stop layer;
an epitaxial source/drain region in the fin, the epitaxial source/drain region extending through the contact etch stop layer;
a metal-semiconductor alloy region contacting upper facets of the epitaxial source/drain region;
a source/drain contact contacting the metal-semiconductor alloy region, lower facets of the epitaxial source/drain region, and a first surface of the contact etch stop layer;
an inter-layer dielectric surrounding the source/drain contact, the inter-layer dielectric contacting the first surface of the contact etch stop layer;
a gate structure on the contact etch stop layer and a sidewall of the fin; and
a gate spacer between the gate structure and the epitaxial source/drain region.

### Claim 17 (depends on 16)

The device of claim 16, wherein the lower facets of the epitaxial source/drain region are free from the contact etch stop layer.

### Claim 18 (depends on 16)

The device of claim 16, wherein the lower facets of the epitaxial source/drain region are free from the metal-semiconductor alloy region.

### Claim 19 (depends on 16)

The device of claim 16, wherein the lower facets of the epitaxial source/drain region are free from the inter-layer dielectric.

### Claim 20 (depends on 16)

The device of claim 16 further comprising:
a void between the epitaxial source/drain region and the contact etch stop layer.