# US 12,119,229 B2 · Method of manufacturing semiconductor structure

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- Number: US 12,119,229 B2
- Document ID: US12119229B2
- Status: Granted
- Kind: B2
- Application number: 17/727,606
- Filed: 2022-04-22
- Published: 2022-08-04
- Granted: 2024-10-15
- Earliest claimed: 2014-02-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Yu-Hsiang Hu; Wei-Yu Chen; Hung-Jui Kuo; Wei-Hung Lin; Ming-Da Cheng; Chung-Shi Liu
- Web page: https://patentgrep.com/patent/US12119229B2

## CPC

- H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/692: Ceramics or glasses
- H10W 70/698: Semiconductor materials that are electrically insulating, e.g. undoped silicon
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10W 74/141: {the encapsulations being on at least the sidewalls of the semiconductor body}
- H10W 74/147: {the encapsulations being multilayered}
- H10W 90/00: Package configurations
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/073: {of die-attach connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H10W 74/014: {using batch processing}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of manufacturing a semiconductor structure includes receiving a die comprising a top surface and a sacrificial layer covering the top surface; disposing a molding surrounding the die; removing the sacrificial layer from the die; disposing a polymer over the die and the molding, wherein the polymer has a first bottom surface contacting the die and a second bottom surface contacting the molding, and the first bottom surface is at a level substantially same as the second bottom surface.

## Claims

### Claim 1

A method of manufacturing a semiconductor structure, comprising:
receiving a die comprising a top surface and a sacrificial layer covering the top surface;
disposing the die on a substrate;
disposing a molding surrounding the die;
removing a portion of the molding to expose a sidewall of the sacrificial laver;
removing the sacrificial layer from the die; and
disposing a polymer over the die and the molding, wherein the polymer has a first bottom surface contacting the die and a second bottom surface contacting the molding, and the first bottom surface is at a level substantially same as the second bottom surface.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first bottom surface of the polymer physically contacts the top surface of the die.

### Claim 3 (depends on 1)

The method of claim 1, wherein the second bottom surface of the polymer physically contacts a top surface of the molding.

### Claim 4 (depends on 3)

The method of claim 3, wherein the polymer is conformal with respect to the top surface of the molding and the top surface of the die.

### Claim 5 (depends on 3)

The method of claim 3, wherein the top surface of the polymer is at a constant level along the top surface of the molding and the top surface of the die.

### Claim 6 (depends on 3)

The method of claim 3, wherein the top surface of the molding is parallel to and aligned with the top surface of the die.

### Claim 7 (depends on 1)

The method of claim 1, further comprising forming a via electrically connected to the die.

### Claim 8 (depends on 7)

The method of claim 7, wherein a height of the via is substantially equal to a thickness of the polymer.

### Claim 9 (depends on 7)

The method of claim 7, wherein the via penetrates through the polymer.

### Claim 10

A method of manufacturing a semiconductor structure, comprising:
receiving a first die and a second die, the first die comprising a first sacrificial layer disposed thereon and the second die comprising a second sacrificial layer disposed thereon, wherein the first die and the second die comprise different heights;
disposing a molding surrounding the first die and the second die;
removing a portion of the molding to expose a sidewall of the first sacrificial layer and a sidewall of the second sacrificial layer;
removing the first sacrificial layer from the first die and the second sacrificial layer from the second; and
disposing a polymer over the first die, the second die and the molding, wherein the polymer has a first bottom surface over the first die, a second bottom surface over the second die and a third bottom surface over the molding, and the second bottom surface is at a level substantially same as the third bottom surface.

### Claim 11 (depends on 10)

The method of claim 10, wherein the first bottom surface is at a level substantially lower than the second bottom surface.

### Claim 12 (depends on 10)

The method of claim 10, wherein a top surface of the molding is at a level substantially higher than the first bottom surface of the polymer.

### Claim 13 (depends on 10)

The method of claim 10, wherein the polymer has a first top surface over the first die and a second top surface over the second die, and the first top surface is at a level substantially lower than the second top surface.

### Claim 14 (depends on 10)

The method of claim 10, further comprising forming a redistribution layer over the polymer.

### Claim 15 (depends on 14)

The method of claim 14, wherein the redistribution layer comprises a first bond pad electrically connected to the first die and a second bond pad electrically connected to the second die.

### Claim 16 (depends on 15)

The method of claim 15, wherein a top surface of the first bond pad is at a level substantially same as a top surface of the second bond pad.

### Claim 17 (depends on 15)

The method of claim 15, wherein the redistribution layer comprises a first conductive trace between the first die and the first bond pad, and a second conductive trace between the second die and the second bond pad, wherein a height of the first conductive trace is greater than a height of the second conductive trace.

### Claim 18

A method of manufacturing a semiconductor structure, comprising:
receiving a first die and a second die, the first die comprising a first sacrificial layer disposed thereon and the second die comprising a second sacrificial layer disposed thereon, wherein a thickness of the first sacrificial layer is different from a thickness of the second sacrificial layer;
disposing a molding surrounding the first die and the second die;
removing the first sacrificial layer from the first die and the second sacrificial layer from the second die; and
disposing a polymer over the first die, the second die and the molding, wherein the polymer has a first surface contacting the first die, a second surface contacting the second die and a third surface contacting the molding, and the second surface is at a level substantially same as the third surface.

### Claim 19 (depends on 18)

The method of claim 18, wherein a top surface of the first sacrificial layer is at a level substantially same as a top surface of the second sacrificial layer before removing the molding.

### Claim 20 (depends on 19)

The method of claim 19, wherein a top surface of the molding is at a level substantially same as the top surface of the first sacrificial layer and the top surface of the second sacrificial layer.