# US 12,119,226 B2 · Method for manufacturing mask structure, semiconductor structure and manufacturing method thereof

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,119,226 B2
- Document ID: US12119226B2
- Status: Granted
- Kind: B2
- Application number: 17/451,967
- Filed: 2021-10-22
- Published: 2022-09-29
- Granted: 2024-10-15
- Earliest claimed: 2021-03-29
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Yexiao Yu; Zhongming Liu; Jia Fang
- Web page: https://patentgrep.com/patent/US12119226B2

## CPC

- H10P 76/405: {characterised by their composition, e.g. multilayer masks}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10B 12/485: {Bit line contacts}
- H10P 14/6902: {composed of carbon, e.g. alpha-C, diamond or hydrogen doped carbon}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/6927: {the material being a silicon oxynitride, e.g. SiON or SiON:H}
- H10P 50/73: {using masks for insulating materials}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for manufacturing the mask structure includes: forming a first mask layer, a first buffer layer, a second mask layer, and a second buffer layer sequentially stacked from bottom to top; patterning the second buffer layer and the second mask layer, as to obtain a first pattern structure, the first pattern structure exposes a part of the first buffer layer; forming a first mask pattern on sidewalls of the first pattern structure; forming a carbon plasma layer as a protective layer on an exposed part of an upper surface of the first buffer layer; removing the first pattern structure; and removing a remaining protective layer.

## Claims

### Claim 1

A method for manufacturing a semiconductor structure, comprising:
providing a substrate;
forming a material layer to be etched on the substrate;
forming a first mask layer, a first buffer layer, a second mask layer, and a second buffer layer sequentially stacked from bottom to top;
patterning the second buffer layer and the second mask layer, as to obtain a first pattern structure, the first pattern structure exposes a part of the first buffer layer;
forming a first mask pattern on sidewalls of the first pattern structure;
forming a carbon plasma layer as a protective layer on an exposed part of an upper surface of first buffer layer on an exposed upper surface of the first buffer layer;
removing the first pattern structure; and
removing a remaining protective layer;
based on the first mask pattern, patterning the first buffer layer and the first mask layer sequentially, as to obtain a target mask pattern; and
based on the target mask pattern, etching the material layer to be etched, as to obtain the semiconductor structure;
wherein a bit line contact hole is formed on the substrate; and forming the material layer to be etched on the substrate comprises:
forming a polysilicon layer in the bit line contact hole and on the substrate;
forming a conductive layer on an upper surface of the polysilicon layer;
forming a dielectric material layer on an upper surface of the conductive layer; and
wherein the target mask pattern is formed on an upper surface of the dielectric material layer.

### Claim 2 (depends on 1)

The method for manufacturing the semiconductor structure according to claim 1, wherein after forming the semiconductor structure, the method further comprises: removing the target mask pattern.

### Claim 3 (depends on 1)

The method for manufacturing the semiconductor structure according to claim 1, wherein based on the target mask pattern, etching the material layer to be etched, as to obtain the semiconductor structure comprises:
based on the target mask pattern, etching the dielectric material layer, the conductive layer, and the polysilicon layer sequentially, as to obtain a bit line structure and a bit line contact structure, and the semiconductor structure is formed by the bit line structure and the bit line contact structure together.

### Claim 4 (depends on 1)

The method for manufacturing the semiconductor structure according to claim 1, wherein forming the polysilicon layer in the bit line contact hole and on the substrate comprises:
forming an intrinsic polysilicon layer in the bit line contact hole and on an upper surface of the substrate; and
doping the intrinsic polysilicon layer in the bit line contact hole, so that the intrinsic polysilicon layer in the bit line contact hole is transformed into a doped polysilicon layer.

### Claim 5 (depends on 1)

The method for manufacturing the semiconductor structure according to claim 1, wherein based on the first mask pattern, patterning the first buffer layer and the first mask layer sequentially, as to obtain the target mask pattern, comprises:
based on the first mask pattern, patterning the first buffer layer, as to obtain a second mask pattern;
removing the first mask pattern;
based on the second mask pattern, patterning the first mask layer; and
removing the second mask pattern, as to obtain the target mask pattern.

### Claim 6

A semiconductor structure, wherein the semiconductor structure is manufactured with a method comprising:
providing a substrate;
forming a material layer to be etched on the substrate;
forming a first mask layer, a first buffer layer, a second mask layer, and a second buffer layer sequentially stacked from bottom to top;
patterning the second buffer layer and the second mask layer, as to obtain a first pattern structure, the first pattern structure exposes a part of the first buffer layer;
forming a first mask pattern on sidewalls of the first pattern structure;
forming a carbon plasma layer as a protective layer on an exposed part of an upper surface of first buffer layer on an exposed upper surface of the first buffer layer;
removing the first pattern structure;
removing a remaining protective layer;
based on the first mask pattern, patterning the first buffer layer and the first mask layer sequentially, as to obtain a target mask pattern; and
based on the target mask pattern, etching the material layer to be etched, as to obtain the semiconductor structure;
wherein a bit line contact hole is formed on the substrate; and forming the material layer to be etched on the substrate comprises:
forming a polysilicon layer in the bit line contact hole and on the substrate;
forming a conductive layer on an upper surface of the polysilicon layer; and
forming a dielectric material layer on an upper surface of the conductive layer;
wherein the target mask pattern is formed on an upper surface of the dielectric material layer.

### Claim 7 (depends on 6)

The semiconductor structure according to claim 6, wherein after forming the semiconductor structure, the method further comprises: removing the target mask pattern.

### Claim 8 (depends on 6)

The semiconductor structure according to claim 6, wherein based on the target mask pattern, etching the material layer to be etched, as to obtain the semiconductor structure comprises:
based on the target mask pattern, etching the dielectric material layer, the conductive layer, and the polysilicon layer sequentially, as to obtain a bit line structure and a bit line contact structure, and the semiconductor structure is formed by the bit line structure and the bit line contact structure together.