# US 12,119,225 B2 · Oxide semiconductor sputtering target and method of fabricating thin-film transistor using same

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- Number: US 12,119,225 B2
- Document ID: US12119225B2
- Status: Granted
- Kind: B2
- Application number: 17/841,270
- Filed: 2022-06-15
- Published: 2022-12-29
- Granted: 2024-10-15
- Earliest claimed: 2021-06-23
- Assignees: KV Materials Co., Ltd.
- Applicants: KV Materials Co., Ltd.
- Inventors: Shinhyuk Kang; Jeonghyun Moon; Kangmin Ok
- Web page: https://patentgrep.com/patent/US12119225B2

## CPC

- H10P 14/22: using physical deposition, e.g. vacuum deposition or sputtering
- C23C 14/08: Oxides (C23C14/10 takes precedence)
- C23C 14/3414: {Metallurgical or chemical aspects of target preparation, e.g. casting, powder metallurgy}
- H01J 37/3426: {Material}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10P 14/3238: {being insulating materials}
- H10P 14/3426: {Oxides}
- H10P 14/3434: {being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424)}
- C23C 14/3407: {Cathode assembly for sputtering apparatus, e.g. Target}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04)
- H01J: ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS (spark-gaps H01T; electric arc lamps H05B31/00; particle accelerators H05H)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An oxide semiconductor sputtering target used in a sputtering process to deposit an active layer of a TFT. The oxide semiconductor sputtering target is formed from a material based on a composition of In, Sn, Ga, Zn, and O. The material contains gallium oxide, tin oxide, zinc oxide, and indium oxide. The In, Sn, Ga, and Zn contents are in ranges of 60% to 80%, 0.5% to 8%, 5% to 15%, and 10% to 30% by weight with respect to the weight of In+Sn+Ga+Zn, respectively. A method of fabricating a TFT includes depositing an active layer using the oxide semiconductor sputtering target. Such a TFT is used in a liquid crystal display (LCD), an organic light-emitting display, an electroluminescence display, and the like.

## Claims

### Claim 1

An oxide semiconductor sputtering target used in a sputtering process to deposit an active layer of a thin-film transistor, comprising:
a material based on a composition of In, Sn, Ga, Zn, and O,
wherein the material comprises gallium oxide, tin oxide, zinc oxide, and indium oxide, wherein In, Sn, Ga, and Zn contents are in ranges of 60% to 80%, 0.5% to 8%, 5% to 15%, and 10% to 30% by weight with respect to the weight of In+Sn+Ga+Zn, respectively.

### Claim 2 (depends on 1)

The oxide semiconductor sputtering target of claim 1, wherein the In, Sn, Ga, and Zn contents are in ranges of 65% to 75%, 1% to 5%, 7% to 13%, and 10% to 20% by weight with respect to the weight of In+Sn+Ga+Zn, respectively.

### Claim 3 (depends on 1)

The oxide semiconductor sputtering target of claim 1, wherein a weight ratio of Sn with respect to In is in a range of 0.03 to 0.15.

### Claim 4 (depends on 1)

The oxide semiconductor sputtering target of claim 1, wherein a total of the Ga and Zn contents is in a range of 20% to 40% by weight with respect to the weight of In+Sn+Ga+Zn.

### Claim 5 (depends on 1)

The oxide semiconductor sputtering target of claim 1, wherein a weight ratio of Ga with respect to Ga+Zn is 0.6 or less.

### Claim 6 (depends on 1)

A method of fabricating a thin-film transistor, the method comprising depositing an active layer using the oxide semiconductor sputtering target of claim 1.

### Claim 7 (depends on 6)

The method of claim 6, further comprising heat-treating the active layer at a temperature in a range of 200° ° C. to 400° ° C. after depositing the active layer.

### Claim 8 (depends on 6)

The method of claim 6, wherein the thin-film transistor is provided in a liquid crystal display device or an organic light-emitting display device.

### Claim 9 (depends on 6)

The method of claim 6, wherein the In, Sn, Ga, and Zn contents are in ranges of 65% to 75%, 1% to 5%, 7% to 13%, and 10% to 20% by weight with respect to the weight of In+Sn+Ga+Zn, respectively.

### Claim 10 (depends on 6)

The method of claim 6, wherein a weight ratio of Sn with respect to In is in a range of 0.03 to 0.15.

### Claim 11 (depends on 6)

The method of claim 6, wherein a total of the Ga and Zn contents is in a range of 20% to 40% by weight with respect to the weight of In+Sn+Ga+Zn.

### Claim 12 (depends on 6)

The method of claim 6, wherein a weight ratio of Ga with respect to Ga+Zn is 0.6 or less.