# US 12,119,083 B2 · Drive circuit, method for driving drive circuit, and memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,119,083 B2 - Document ID: US12119083B2 - Status: Granted - Kind: B2 - Application number: 17/874,813 - Filed: 2022-07-27 - Published: 2023-11-16 - Granted: 2024-10-15 - Earliest claimed: 2022-05-13 - Assignees: Changxin Memory Technologies, Inc. - Applicants: Changxin Memory Technologies, Inc. - Inventors: Shuhao Zhang; Ning Li - Web page: https://patentgrep.com/patent/US12119083B2 ## CPC - G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines - H03K 19/0013: {in field effect transistor circuits} - G11C 5/14: Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} - G11C 7/1096: {Write circuits, e.g. I/O line write drivers} - G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines - G11C 8/14: Word line organisation; Word line lay-out - G11C 11/408: Address circuits - G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge} - G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches - G11C 16/34: Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention - H03K 3/356113: {using additional transistors in the input circuit} - H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) - G11C: STATIC STORES (semiconductor memory devices H10B) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A drive circuit, a method for driving the drive circuit and a memory are provided. The drive circuit includes a word line drive circuit and a first control circuit. The word line drive circuit includes an input terminal, an output terminal and at least one N-type transistor. The word line drive circuit is configured to provide an output signal to the output terminal according to an input signal received by the input terminal. The first control circuit is configured to pull down, in response to the input signal being a first control signal, a voltage of a substrate terminal of the at least one N-type transistor in the word line drive circuit, to reduce a leakage current of the at least one N-type transistor. ## Claims ### Claim 1 A drive circuit, comprising: a word line drive circuit, comprising an input terminal and an output terminal and configured to provide an output signal to the output terminal according to an input signal received by the input terminal, the word line drive circuit comprising at least one N-type transistor; and a first control circuit, configured to pull down, in response to the input signal being a first control signal, a voltage of a substrate terminal of the at least one N-type transistor to reduce a leakage current of the at least one N-type transistor; wherein the first control circuit comprises a second P-type transistor, and the second P-type transistor comprises a gate electrode connected to the input terminal of the word line drive circuit, a first electrode connected to the substrate terminal of the at least one N-type transistor, and a second electrode connected to a third signal terminal, wherein the third signal terminal is configured to provide a third voltage in a case where the second P-type transistor is turned on. ### Claim 2 (depends on 1) The drive circuit of claim 1, wherein the third voltage is lower than zero voltage. ### Claim 3 (depends on 1) The drive circuit of claim 1, wherein the word line drive circuit comprises a first P-type transistor and a first N-type transistor, a gate electrode of the first P-type transistor and a gate electrode of the first N-type transistor are connected to each other and used as the input terminal of the word line drive circuit, a first electrode of the first P-type transistor and a first electrode of the first N-type transistor are connected to each other and used as the output terminal of the word line drive circuit, and a substrate terminal of the first N-type transistor is connected to the first electrode of the second P-type transistor. ### Claim 4 (depends on 3) The drive circuit of claim 3, wherein a second electrode of the first P-type transistor is connected to a first signal terminal, and a second electrode of the first N-type transistor is connected to a second signal terminal, wherein the first signal terminal is configured to provide a first voltage in a case where the first P-type transistor is turned on, and the second signal terminal is configured to provide a second voltage in a case where the first N-type transistor is turned on, and the first voltage is greater than the second voltage. ### Claim 5 (depends on 4) The drive circuit of claim 4, wherein the word line drive circuit further comprises: a second N-type transistor, comprising a first electrode connected to the output terminal of the word line drive circuit, a second electrode connected to the second electrode of the first N-type transistor, and a gate electrode connected to the input terminal or a control signal terminal of the word line drive circuit, wherein the control signal terminal is configured to provide a control signal in phase with the input signal. ### Claim 6 (depends on 5) The drive circuit of claim 5, wherein a substrate terminal of the second N-type transistor is connected to the first electrode of the second P-type transistor. ### Claim 7 (depends on 5) The drive circuit of claim 5, further comprising: a second control circuit, configured to pull up, in response to the input signal being a second control signal, the voltage of the substrate terminal of the at least one N-type transistor to reduce a threshold voltage of the at least one N-type transistor, wherein a level of the second control signal is different from that of the first control signal. ### Claim 8 (depends on 7) The drive circuit of claim 7, wherein the level of the first control signal is lower than that of the second control signal. ### Claim 9 (depends on 7) The drive circuit of claim 7, wherein the second control circuit comprises a third N-type transistor, and the third N-type transistor comprises a gate electrode connected to the input terminal of the word line drive circuit, a first electrode connected to the substrate terminal of the at least one N-type transistor, and a second electrode connected to a fourth signal terminal, wherein the fourth signal terminal is configured to provide a fourth voltage in a case where the third N-type transistor is turned on. ### Claim 10 (depends on 9) The drive circuit of claim 9, wherein the fourth voltage is greater than the third voltage. ### Claim 11 (depends on 9) The drive circuit of claim 9, wherein the first electrode of the third N-type transistor is connected to the substrate terminal of the first N-type transistor and the substrate terminal of the second N-type transistor. ### Claim 12 (depends on 1) The drive circuit of claim 1, wherein the input terminal of the word line drive circuit is connected to a main word line, and the output terminal of the word line drive circuit is connected to a word line. ### Claim 13 A memory, comprising a drive circuit and a bank, the bank comprising one or a plurality of memory cells, the drive circuit comprising: a word line drive circuit, comprising an input terminal and an output terminal and configured to provide an output signal to the output terminal according to an input signal received by the input terminal, the word line drive circuit comprising at least one N-type transistor; and a first control circuit, configured to pull down, in response to the input signal being a first control signal, a voltage of a substrate terminal of the at least one N-type transistor to reduce a leakage current of the at least one N-type transistor; wherein the first control circuit comprises a second P-type transistor, and the second P-type transistor comprises a gate electrode connected to the input terminal of the word line drive circuit, a first electrode connected to the substrate terminal of the at least one N-type transistor and a second electrode connected to a third signal terminal, wherein the third signal terminal is configured to provide a third voltage in a case where the second P-type transistor is turned on; in a case where a running state of the bank is a bank active state, the first control circuit pulls down the voltage of the substrate terminal of the at least one N-type transistor in the word line drive circuit. ### Claim 14 (depends on 1) A method for driving a drive circuit of claim 1, comprising: providing an input signal to an input terminal of a word line drive circuit in the drive circuit, to enable an output terminal of the word line drive circuit to provide an output signal; and pulling down, in response to the input signal being a first control signal, a voltage of a substrate terminal of at least one N-type transistor in the word line drive circuit to reduce a leakage current of the at least one N-type transistor. ### Claim 15 (depends on 14) The method of claim 14, wherein the drive circuit further comprises: a second control circuit, configured to pull up, in response to the input signal being a second control signal, the voltage of the substrate terminal of the at least one N-type transistor to reduce a threshold voltage of the at least one N-type transistor, wherein a level of the second control signal is different from that of the first control signal, wherein the method further comprises: pulling up, in response to the input signal being the second control signal, the voltage of the substrate terminal of the at least one N-type transistor to reduce the threshold voltage of the at least one N-type transistor. ### Claim 16 (depends on 15) The method of claim 15, wherein the word line drive circuit comprises a first P-type transistor and a first N-type transistor, a gate electrode of the first P-type transistor and a gate electrode of the first N-type transistor are connected to each other and used as the input terminal of the word line drive circuit, and a first electrode of the first P-type transistor and a first electrode of the first N-type transistor are connected to each other and used as the output terminal of the word line drive circuit; wherein the second control circuit comprises a third N-type transistor, and the third N-type transistor comprises a gate electrode connected to the input terminal of the word line drive circuit, a first electrode connected to the substrate terminal of the first N-type transistor, and a second electrode connected to a fourth signal terminal, the fourth signal terminal being configured to provide a fourth voltage in a case where the third N-type transistor is turned on; wherein pulling up, in response to the input signal being the second control signal, the voltage of the substrate terminal of the at least one N-type transistor to reduce the threshold voltage of the at least one N-type transistor comprises: controlling, in response to the input signal being the second control signal, the third N-type transistor to be turned on, to enable the substrate terminal of the first N-type transistor to be connected to the fourth signal terminal to reduce the threshold voltage of the first N-type transistor. ### Claim 17 (depends on 15) The method of claim 15, wherein the word line drive circuit comprises a first P-type transistor, a first N-type transistor, and a second N-type transistor, a gate electrode of the first P-type transistor and a gate electrode of the first N-type transistor are connected to each other and used as the input terminal of the word line drive circuit, a first electrode of the first P-type transistor and a first electrode of the first N-type transistor are connected to each other and used as the output terminal of the word line drive circuit, a gate electrode of the second N-type transistor is connected to the input terminal or a control signal terminal of the word line drive circuit, a first electrode of the second N-type transistor is connected to the output terminal of the word line drive circuit, a second electrode of the second N-type transistor is connected to the second electrode of the first N-type transistor, and the control signal terminal is configured to provide a control signal in phase with the input signal, wherein the second control circuit comprises a third N-type transistor, and the third N-type transistor comprises a gate electrode connected to the input terminal of the word line drive circuit, a first electrode connected to at least one of the substrate terminal of the first N-type transistor or the substrate terminal of the second N-type transistor, and a second electrode connected to a fourth signal terminal, the fourth signal terminal being configured to provide a fourth voltage in a case where the third N-type transistor is turned on; wherein pulling up, in response to the input signal being the second control signal, the voltage of the substrate terminal of the at least one N-type transistor to reduce the threshold voltage of the at least one N-type transistor comprises: controlling, in response to the input signal being the second control signal, the third N-type transistor to be turned on, to enable at least one of the substrate terminal of the first N-type transistor or the substrate terminal of the second N-type transistor to be connected to the fourth signal terminal, and pulling up the voltage of the substrate terminal of at least one of the first N-type transistor or the second N-type transistor to reduce the threshold voltage of at least one of the first N-type transistor or the second N-type transistor. ### Claim 18 (depends on 14) The method of claim 14, wherein the word line drive circuit comprises a first P-type transistor and a first N-type transistor, a gate electrode of the first P-type transistor and a gate electrode of the first N-type transistor are connected to each other and used as the input terminal of the word line drive circuit, and a first electrode of the first P-type transistor and a first electrode of the first N-type transistor are connected to each other and used as the output terminal of the word line drive circuit; wherein a first control circuit in the drive circuit comprises a second P-type transistor, and the second P-type transistor comprises a gate electrode connected to the input terminal of the word line drive circuit, a first electrode connected to a substrate terminal of the first N-type transistor, and a second electrode connected to a third signal terminal, the third signal terminal being configured to provide a third voltage in a case where the second P-type transistor is turned on; wherein pulling down, in response to the input signal being the first control signal, the voltage of the substrate terminal of the at least one N-type transistor to reduce the leakage current of the at least one N-type transistor comprises: controlling, in response to the input signal being the first control signal, the second P-type transistor to be turned on, to enable the substrate terminal of the first N-type transistor to be connected to the third signal terminal, and pulling down the voltage of the substrate terminal of the first N-type transistor to reduce the leakage current of the first N-type transistor. ### Claim 19 (depends on 14) The method of claim 14, wherein the word line drive circuit comprises a first P-type transistor, a first N-type transistor, and a second N-type transistor, a gate electrode of the first P-type transistor and a gate electrode of the first N-type transistor are connected to each other and used as the input terminal of the word line drive circuit, a first electrode of the first P-type transistor and a first electrode of the first N-type transistor are connected to each other and used as the output terminal of the word line drive circuit, a gate electrode of the second N-type transistor is connected to the input terminal or a control signal terminal of the word line drive circuit, a first electrode of the second N-type transistor is connected to the output terminal of the word line drive circuit, a second electrode of the second N-type transistor is connected to the second electrode of the first N-type transistor, and the control signal terminal is configured to provide a control signal in phase with the input signal; wherein a first control circuit comprises a second P-type transistor, and the second P-type transistor comprises a gate electrode connected to the input terminal of the word line drive circuit, a first electrode connected to at least one of a substrate terminal of the first N-type transistor or a substrate terminal of the second N-type transistor, and a second electrode connected to a third signal terminal, the third signal terminal being configured to provide a third voltage in a case where the second P-type transistor is turned on; wherein pulling down, in response to the input signal being the first control signal, the voltage of the substrate terminal of the at least one N-type transistor to reduce the leakage current of the at least one N-type transistor comprises: controlling, in response to the input signal being the first control signal, the second P-type transistor to be turned on, to enable at least one of the substrate terminal of the first N-type transistor or the substrate terminal of the second N-type transistor to be connected to the third signal terminal, and pulling down the voltage of the substrate terminal of at least one of the first N-type transistor or the second N-type transistor to reduce the leakage current of at least one of the first N-type transistor or the second N-type transistor.