# US 12,119,081 B2 · Semiconductor storage device and control method of semiconductor storage device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,119,081 B2 - Document ID: US12119081B2 - Status: Granted - Kind: B2 - Application number: 18/151,589 - Filed: 2023-01-09 - Published: 2023-09-14 - Granted: 2024-10-15 - Earliest claimed: 2022-03-14 - Assignees: Fujitsu Limited - Applicants: Fujitsu Limited - Inventors: Hiroshi Nakadai - Web page: https://patentgrep.com/patent/US12119081B2 ## CPC - G11C 7/14: Dummy cell management; Sense reference voltage generators - G11C 11/419: Read-write [R-W] circuits - G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines - G11C 29/021: {in voltage or current generators} - G11C 29/028: {with adaption or trimming of parameters} - G11C 29/12005: {comprising voltage or current generators} - G11C 29/56: External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor - G11C 7/1096: {Write circuits, e.g. I/O line write drivers} - G11C 2029/5002: {Characteristic} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A semiconductor storage device includes: a storage element that holds data; a bit line that is coupled to the storage element and in which step-down to reference voltage causes data held in the storage element to be inverted, a first step-down circuit that steps down bit line voltage to a first predetermined value equal to or below the reference voltage, the bit line voltage being voltage applied to the bit line; and a control circuit that detects a first voltage change based on a first output from a first inverter which has a voltage dependence of an occurring delay and a second output from a second inverter in which a voltage dependence of an occurring delay is larger than that of the first inverter, and that controls a step-down amount of the bit line voltage by the first step-down circuit depending on an amount of the detected first voltage change. ## Claims ### Claim 1 A semiconductor storage device comprising: a storage element that holds data; a bit line that is coupled to the storage element and in which step-down to reference voltage causes data held in the storage element to be inverted, a first step-down circuit that steps down bit line voltage to a first predetermined value equal to or below the reference voltage, the bit line voltage being voltage applied to the bit line; and a control circuit that detects a first voltage change based on a first output from a first inverter which has a voltage dependence of an occurring delay and a second output from a second inverter in which a voltage dependence of an occurring delay is larger than that of the first inverter, and that controls a step-down amount of the bit line voltage by the first step-down circuit depending on an amount of the detected first voltage change. ### Claim 2 (depends on 1) The semiconductor storage device according to claim 1, wherein in the control circuit, a predetermined signal having a voltage change at a specific timing is inputted into each of the first inverter and the second inverter, and the control circuit calculates a difference between a timing of the first output with respect to the voltage change of the predetermined signal and a timing of the second output with respect to the voltage change of the predetermined signal, as the amount of the detected first voltage change, and causes the first step-down circuit to step down the bit line voltage to the first predetermined value for a period of the difference. ### Claim 3 (depends on 1) The semiconductor storage device according to claim 1, further comprising a holding circuit that causes the first step-down circuit to keep on stepping down the bit line voltage to the first predetermined value, for a predetermined period. ### Claim 4 (depends on 1) The semiconductor storage device according to claim 1, further comprising a second step-down circuit that further steps down the bit line voltage from the first predetermined value by a second predetermined value, wherein the control circuit further includes a third inverter that is coupled to the second inverter in series and in which a voltage dependence of an occurring delay is larger than that of the first inverter, controls the step-down amount of the bit line voltage by the first step-down circuit, based on the first output and the second output, and detects a second voltage change based on the first output and a third output from the third inverter, and controls a step-down amount of the bit line voltage by the second step-down circuit, depending on an amount of the detected second voltage change. ### Claim 5 (depends on 1) The semiconductor storage device according to claim 1, wherein the control circuit further includes a fourth inverter that is coupled to the second inverter in series and in which a voltage dependence of an occurring delay is larger than that in the first inverter, selects one of the second output and a fourth output from the fourth inverter, when the second output is selected, controls the step-down amount of the bit line voltage by the first step-down circuit depending on the amount of the first voltage change, and when the fourth output is selected, detects a third voltage change based on the first output and the fourth output, and controls the step-down amount of the bit line voltage by the first step-down circuit depending on an amount of the detected third voltage change. ### Claim 6 (depends on 1) The semiconductor storage device according to claim 1, further comprising a test execution circuit that detects a fourth voltage change based on a fifth output from a fifth inverter which has a voltage dependence of an occurring delay and a sixth output from a sixth inverter in which a voltage dependence of an occurring delay is larger than that of the fifth inverter, and that determines the step-down amount of the bit line voltage by the first step-down circuit depending on an amount of the detected fourth voltage change, wherein the control circuit controls the step-down amount of the bit line voltage by the first step-down circuit, based on the step-down amount of the bit line voltage determined by the test execution circuit. ### Claim 7 A control method of a semiconductor storage device comprising: stepping down, by a first step-down circuit, a bit line voltage to a first predetermined value equal to or below the reference voltage, the bit line voltage being voltage applied to a bit line that is coupled to the storage element and in which step-down to reference voltage causes data held in a storage element to be inverted; and detecting, by a control circuit, a first voltage change based on a first output from a first inverter which has a voltage dependence of an occurring delay and a second output from a second inverter in which a voltage dependence of an occurring delay is larger than that of the first inverter and controlling a step-down amount of the bit line voltage by the first step-down circuit depending on an amount of the detected first voltage change.