# US 12,119,080 B1 · Extended-burst write training

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,119,080 B1
- Document ID: US12119080B1
- Status: Granted
- Kind: B1
- Application number: 17/717,419
- Filed: 2022-04-11
- Granted: 2024-10-15
- Earliest claimed: 2021-04-19
- Assignees: Cadence Design Systems, Inc.
- Applicants: Cadence Design Systems, Inc.
- Inventors: Sreeja Menon; Nikhil Raghavendra Rao; Srinivas Shanmukha Gundlapalli
- Web page: https://patentgrep.com/patent/US12119080B1

## CPC

- G11C 7/1096: {Write circuits, e.g. I/O line write drivers}
- G11C 7/1063: {Control signal output circuits, e.g. status or busy flags, feedback command signals}
- G11C 7/1066: {Output synchronization}
- G11C 7/1093: {Input synchronization}
- G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A control component transmits a timing strobe and associated write data burst to a memory component, extending the write data burst to include a quantity of successive bits in excess of active edges in the timing strobe to ensure that the write data burst is sampled under worst-case timing skew conditions.

## Claims

### Claim 1

A memory control integrated circuit (IC) comprising:
a command interface to transmit a write command to a memory component; and
a data interface to transmit to the memory component in association with the write command:
a data strobe having a preamble and a first quantity of data-timing transitions that immediately follow the preamble; and
a data burst constituted by a second quantity of data symbols transmitted in respective, successive symbol-transmission intervals, the second quantity exceeding the first quantity.

### Claim 2 (depends on 1)

The memory control IC of claim 1 wherein the data interface to transmit the data strobe to the memory component in association with the write command comprises circuitry to commence transmission of the data strobe a predetermined time after transmitting the write command.

### Claim 3 (depends on 1)

The memory control IC of claim 1 wherein the data interface to transmit the data strobe to the memory component comprises circuitry to transmit, in succession, the preamble, the first quantity of data-timing transitions, and a postamble.

### Claim 4 (depends on 1)

The memory control IC of claim 1 further comprising a programmable register to store information indicative of a value by which the second quantity exceeds the first quantity.

### Claim 5 (depends on 1)

The memory control IC of claim 1 wherein the data interface to transmit the data burst constituted by the second quantity of data symbols comprises data-transmit circuitry to transmit a first number of data symbols according to a nominal burst length followed continuously by a second number of data symbols, the first number of data symbols matching the first quantity of data-timing transitions.

### Claim 6 (depends on 5)

The memory control IC of claim 5 wherein the data-transmit circuitry additionally transmits a third number of data symbols immediately prior to transmitting the first number of data symbols, the first, second and third numbers of data symbols collectively constituting the second quantity of data symbols.

### Claim 7 (depends on 1)

The memory control IC of claim 1 wherein each of the data symbols is constituted by a respective bit.

### Claim 8 (depends on 1)

The memory control IC of claim 1 wherein the data interface to transmit the data burst constituted by the second quantity of data symbols comprises data-transmit circuitry to (i) transmit the data burst constituted by the second quantity of data symbols during operation of the memory control component in a write-training mode, and (ii) transmit a data burst constituted by data symbols equal in number to the first quantity of data-timing transitions during operation of the memory control IC in an operating mode other than the write-training mode.

### Claim 9 (depends on 8)

The memory control IC of claim 8 further comprising a programmable register to store a mode value in a first state to render the memory control IC into the write-training mode and to store a mode value in a state other than the first state to render the memory control IC into an operating mode other than the write-training mode.

### Claim 10 (depends on 1)

The memory control IC of claim 1 wherein at least one of the command interface and the data interface comprises circuitry to transmit a register programming command/operand to the memory component, the register programming command/operand instructing the memory component to respond to the write command by storing at least a portion of the data burst within a training register instead of a core storage array of the memory component.

### Claim 11

A method of operation within a memory control component, the method comprising:
transmitting a write command to a memory component;
transmitting a data strobe to the memory component in association with the write command, the data strobe having a preamble and a first quantity of data-timing transitions that immediately follow the preamble; and
transmitting a data burst to the memory component in association with the write command, the data burst constituted by a second quantity of data symbols transmitted in respective, successive symbol-transmission intervals, the second quantity exceeding the first quantity.

### Claim 12 (depends on 11)

The method of claim 11 wherein transmitting the data strobe to the memory component in association with the write command comprises commencing transmission of the data strobe a predetermined time after transmitting the write command.

### Claim 13 (depends on 11)

The method of claim 11 wherein transmitting the data strobe to the memory component comprises transmitting, in succession, the preamble, the first quantity of data-timing transitions, and a postamble.

### Claim 14 (depends on 11)

The method of claim 11 further comprising programming one or more fields of a programmable register with information indicative of a value by which the second quantity exceeds the first quantity.

### Claim 15 (depends on 11)

The method of claim 11 wherein transmitting the data burst constituted by the second quantity of data symbols comprises transmitting a first number of data symbols according to a nominal burst length followed continuously by a second number of data symbols, the first number of data symbols matching the first quantity of data-timing transitions.

### Claim 16 (depends on 15)

The method of claim 15 wherein transmitting the data burst constituted by the second quantity of data symbols further comprises transmitting a third number of data symbols immediately prior to transmitting the first number of data symbols.

### Claim 17 (depends on 11)

The method of claim 11 wherein each of the data symbols is constituted by a respective bit.

### Claim 18 (depends on 11)

The method of claim 11 wherein transmitting the data burst constituted by the second quantity of data symbols comprises transmitting the data burst constituted by the second quantity of data symbols during operation of the memory control component in a write-training mode, the method further comprising transmitting a data burst constituted by data symbols equal in number to the first quantity of data-timing transitions during operation of the memory control component in a mode other than the write-training mode.

### Claim 19 (depends on 18)

The method of claim 18 further comprising storing a mode value within a control register of the memory control component to transition the memory control component to the write-training mode.

### Claim 20 (depends on 11)

The method of claim 11 further comprising transmitting a register programming command/operand to the memory component to instruct the memory component to respond to the write command by storing at least a portion of the data burst within a training register instead of a core storage array of the memory component.