# US 12,119,076 B2 · Semiconductor integrated circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,119,076 B2 - Document ID: US12119076B2 - Status: Granted - Kind: B2 - Application number: 17/679,924 - Filed: 2022-02-24 - Published: 2023-01-12 - Granted: 2024-10-15 - Earliest claimed: 2021-07-06 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Takayuki Miyazaki; Yuki Ishizaki - Web page: https://patentgrep.com/patent/US12119076B2 ## CPC - G11C 7/065: {Differential amplifiers of latching type} - G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor} - G11C 7/1057: {Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load} - G11C 7/106: {Data output latches} - G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines - G11C 2029/0411: {Online error correction} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A semiconductor integrated circuit includes a plurality of sense amplifier units including a first group of sense amplifier units and a second group of sense amplifier units, a first data bus, a second data bus, a transfer circuit between the first data bus and the second data bus, and a data latch connected to the second data bus and to the first data bus through the transfer circuit and the second data bus. Each sense amplifier unit is connected to one of the bit lines. The first data bus is connected to each of the sense amplifier units in the first group. The second data bus is connected to each of the sense amplifier units in the second group. The transfer circuit controls the transfer of data between the first data bus and the second data bus in both directions. ## Claims ### Claim 1 A semiconductor integrated circuit configured to transmit and receive data to and from a plurality of memory cells associated with word lines and bit lines in a semiconductor memory device, the semiconductor integrated circuit comprising: a plurality of sense amplifier units, including a first group of sense amplifier units and a second group of sense amplifier units, wherein each of the sense amplifier units is connected to one of the bit lines; a first data bus connected to each of the sense amplifier units in the first group; a second data bus connected to each of the sense amplifier units in the second group; a transfer circuit that is connected between the first data bus and the second data bus and controlled to invert and transfer data in a first direction from the first data bus to the second data bus and to transfer data in a second direction from the second data bus to the first data bus without inversion, the transfer circuit including an inverter circuit that is connected between the first data bus and the second data bus and is controlled to enable transmission of data from the first data bus to the second data bus therethrough during the data transfer in the first direction and to block the transmission of data from the first data bus to the second data bus therethrough during the data transfer in the second direction; and a data latch that is connected to the second data bus, and to the first data bus through the second data bus and the transfer circuit. ### Claim 2 (depends on 1) The semiconductor integrated circuit according to claim 1, wherein the transfer circuit further includes a first switch circuit that is connected in parallel with the inverter circuit between the first data bus and the second data bus, and is controlled to block the transmission of data therethrough during the data transfer in the first direction and to enable the transmission of data therethrough during the data transfer in the second direction. ### Claim 3 (depends on 2) The semiconductor integrated circuit according to claim 2, wherein the inverter circuit includes an inverting buffer having an input terminal connected to the first data bus and an output terminal connected to the second data bus, and a second switch circuit that is controlled to enable transmission of data from the first data bus to the second data bus through the inverting buffer during the data transfer in the first direction and to block the transmission of data from the first data bus to the second data bus through the inverting buffer during the data transfer in the second direction. ### Claim 4 (depends on 3) The semiconductor integrated circuit according to claim 3, wherein the second switch circuit includes a MOS transistor, and a gate voltage of the MOS transistor is higher than a power supply voltage that is supplied to the inverter circuit. ### Claim 5 (depends on 3) The semiconductor integrated circuit according to claim 3, wherein the inverting buffer includes a complementary MOS inverter, and a voltage amplitude at the input terminal of the inverting buffer is larger than a power supply voltage that is supplied to the inverter circuit. ### Claim 6 (depends on 3) The semiconductor integrated circuit according to claim 3, wherein the inverting buffer includes a complementary MOS inverter, and a gate voltage of a MOS transistor of the second switch circuit is larger than a voltage amplitude at the input terminal of the inverting buffer. ### Claim 7 (depends on 3) The semiconductor integrated circuit according to claim 3, wherein a threshold voltage of a MOS transistor of the second switch circuit is lower than a threshold voltage of a MOS transistor of the inverting buffer. ### Claim 8 (depends on 1) The semiconductor integrated circuit according to claim 1, wherein, during an operation that includes data transmission through the first data bus and the second data bus, a voltage amplitude of data transmitted through the first data bus is larger than a voltage amplitude of data transmitted through the second data bus. ### Claim 9 (depends on 1) The semiconductor integrated circuit according to claim 1, wherein, during an operation that includes data transmission through the first data bus and the second data bus, the sense amplifier units in the first group and the sense amplifier units in the second group simultaneously read the data from the memory cells of the plurality of memory cells that are respective thereto, and the data read by the sense amplifier units in the first group and the data read by the sense amplifier units in the second group are transferred to the data latch at different timings. ### Claim 10 (depends on 9) The semiconductor integrated circuit according to claim 9, wherein, during the operation that includes data transmission through the first data bus and the second data bus, a time period during which the sense amplifier units in the first group output the data to the first data bus and a time period during which the sense amplifier units in the second group output the data to the second data bus at least partially overlap. ### Claim 11 (depends on 9) The semiconductor integrated circuit according to claim 9, wherein, during the operation that includes data transmission through the first data bus and the second data bus, after the data has been output from the sense amplifier units in the second group to the second data bus, the data is output from the sense amplifier units in the first group to the first data bus. ### Claim 12 (depends on 1) The semiconductor integrated circuit according to claim 1, wherein, during an operation that includes data transmission through the first data bus and the second data bus, the sense amplifier units in the first group output data after inversion, and the sense amplifier units in the second group output data without inversion. ### Claim 13 (depends on 1) The semiconductor integrated circuit according to claim 1, wherein the sense amplifier units in the first and second groups each include a latch circuit having a first terminal and a second terminal, and each of the sense amplifier units in the first group outputs data through the first terminal of the latch circuit corresponding thereto and each of the sense amplifier units in the second group outputs data through the second terminal of the latch circuit corresponding thereto. ### Claim 14 (depends on 1) The semiconductor integrated circuit according to claim 1, wherein the data latch includes a latch circuit including first and second terminals, and the data output from the sense amplifier units in the first group is received at the first terminal and the data output from the sense amplifier units in the second group is received at the second terminal. ### Claim 15 (depends on 1) The semiconductor integrated circuit according to claim 1, wherein, during an operation that includes data transmission through the first data bus and the second data bus, the data is output from the sense amplifier units in the first group to the first data bus, during a period in which the data is transmitted from the data latch to the sense amplifier units in the second group via the second data bus. ### Claim 16 (depends on 1) The semiconductor integrated circuit according to claim 1, wherein an instruction to cause the sense amplifier units in the first group to read the data from the memory cells of the plurality of memory cells that are respective thereto is different from an instruction to cause the sense amplifier units in the second group to read the data from the memory cells of the plurality of memory cells that are respective thereto. ### Claim 17 (depends on 16) The semiconductor integrated circuit according to claim 16, wherein in a case of a first read operation, addresses corresponding to the memory cells of the plurality of the memory cells associated with a group of the bit lines that are connected to the sense amplifier units in the second group are designated by a first read instruction, and in a case of a second read operation that is slower than the first read operation, addresses corresponding to the memory cells of the plurality of the memory cells associated with a group of the bit lines that are connected to the sense amplifier units in the first group are designated by a second read instruction. ### Claim 18 (depends on 1) The semiconductor integrated circuit according to claim 1, wherein the bit lines connected to the sense amplifier units in the first group and the bit lines connected to the sense amplifier units in the second group are alternately arranged. ### Claim 19 A method of transmitting data from a plurality of sense amplifier units of a semiconductor integrated circuit to a data latch of the semiconductor integrated circuit over a first data bus that is connected to a first group of the sense amplifier units and a second data bus that is connected to a second group of the sense amplifier units, said method comprising: controlling a transfer circuit that is connected between the first data bus and the second data bus to invert and transfer data in a first direction from the first data bus to the second bus and to transfer data in a second direction from the second data bus to the first data bus without inversion, wherein the transfer circuit includes an inverter circuit that is connected between the first data bus and the second data bus and is controlled to enable transmission of data from the first data bus to the second data bus therethrough during the data transfer in the first direction and to block the transmission of data from the first data bus to the second data bus therethrough during the data transfer in the second direction. ### Claim 20 (depends on 19) The method according to claim 19, wherein the transfer circuit includes a switch circuit that is connected in parallel with the inverter circuit between the first data bus and the second data bus, and is controlled to be turned off when transferring data from the sense amplifier units in the first group to the data latch through the first data bus and the second data bus, and to be turned on when transferring data from the data latch to the sense amplifier units in the first group through the second data bus and the first data bus.