# US 12,119,075 B2 · Efficient soft decoding of error correction code via extrinsic bit information > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,119,075 B2 - Document ID: US12119075B2 - Status: Granted - Kind: B2 - Application number: 18/185,198 - Filed: 2023-03-16 - Published: 2024-09-19 - Granted: 2024-10-15 - Earliest claimed: 2023-03-16 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Avi Steiner; Ofir Kanter; Yasuhiko Kurosawa - Web page: https://patentgrep.com/patent/US12119075B2 ## CPC - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - G11C 29/021: {in voltage or current generators} - G11C 29/022: {in I/O circuitry} - G11C 29/024: {in decoders} - G11C 29/028: {with adaption or trimming of parameters} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Aspects of this technical solution can include selecting a plurality of memory locations at a memory device, the memory locations corresponding to a first page including a first plurality of bits and a second page including a second plurality of bits, modifying, based on the first plurality of bits and the second plurality of bits, a first voltage threshold corresponding to an estimated read voltage for the first plurality of bits, allocating, to a voltage range bounded by the first voltage threshold, a log-likelihood ratio (LLR), and decoding, based on the LLR corresponding to the voltage range, the first plurality of bits. ## Claims ### Claim 1 A computer-implemented method of soft correction in a memory device, the computer-implemented method comprising: selecting a plurality of memory locations at a memory device, the memory locations corresponding to a first page including a first plurality of bits and a second page including a second plurality of bits; modifying, based on the first plurality of bits and the second plurality of bits, a first voltage threshold corresponding to an estimated read voltage for the first plurality of bits; allocating, to a voltage range bounded by the first voltage threshold, a log-likelihood ratio (LLR); and decoding, based on the LLR corresponding to the voltage range, the first plurality of bits. ### Claim 2 (depends on 1) The method of claim 1, further comprising: generating, based on the first plurality of bits and the second plurality of bits, a histogram corresponding to the first plurality of bits; and modifying, based on the first voltage threshold corresponding to the histogram, one or more of the first voltage threshold and the second voltage threshold, the voltage range bounded by the first voltage threshold and the second voltage threshold. ### Claim 3 (depends on 1) The method of claim 1, further comprising: modifying, based on the first voltage threshold and a second voltage threshold corresponding to a read operation of the first plurality of bits, one or more of the first voltage threshold and the second voltage threshold. ### Claim 4 (depends on 3) The method of claim 3, further comprising: obtaining, during a sequential read, one or more of extrinsic page information including the second page, the LLR and ICI information; generating a magnitude of the LLR in response to and based on one or more of a soft sampling operation, a voltage bounded by the voltage range, the second voltage threshold, the first plurality of bits, and the second plurality of bits, the LLR having a first confidence based on the first plurality of bits and the second plurality of bits greater than a second confidence based on the first plurality of bits and excluding the second plurality of bits. ### Claim 5 (depends on 3) The method of claim 3, the first voltage threshold corresponding to a first plurality of voltage thresholds, the second voltage threshold corresponding to a second plurality of voltage thresholds, and the voltage ranges corresponding to a plurality of voltage ranges between adjacent ones of the first plurality of voltage thresholds and the second plurality of voltage thresholds. ### Claim 6 (depends on 1) The method of claim 1, further comprising: decoding, based on the first plurality of bits and the second plurality of bits, the first plurality of bits by hard decoding; and modifying the first voltage threshold, in response to an indication of failure corresponding to the decoding of the first plurality of bits by hard decoding. ### Claim 7 (depends on 1) The method of claim 1, further comprising: generating, in response to an indication of failure corresponding to the decoding the first plurality of bits based on the LLR, a third voltage threshold corresponding to the read voltage for the first plurality of bits. ### Claim 8 (depends on 7) The method of claim 7, further comprising: allocating, to a second voltage range bounded by the third voltage threshold, a log-likelihood ratio (LLR); and decoding, based on the LLR corresponding to the second voltage range, the first plurality of bits. ### Claim 9 (depends on 7) The method of claim 7, the first voltage threshold corresponding to a first plurality of voltage thresholds, the third voltage threshold corresponding to a third plurality of voltage thresholds, and the voltage ranges corresponding to a plurality of voltage ranges between adjacent ones of the first plurality of voltage thresholds and the third plurality of voltage thresholds. ### Claim 10 A memory system comprising: a non-volatile memory; and a controller for performing operations of the non-volatile memory, the controller being configured to: select a plurality of memory locations at a memory device, the memory locations corresponding to a first page including a first plurality of bits and a second page including a second plurality of bits; modify, based on the first plurality of bits and the second plurality of bits, a first voltage threshold corresponding to a read voltage for the first plurality of bits; allocate, to a voltage range bounded by the first voltage threshold, a log-likelihood ratio (LLR); and decode, based on the LLR corresponding to the voltage range, the first plurality of bits. ### Claim 11 (depends on 10) The system of claim 10, the controller further configured to: generate, based on the first plurality of bits and the second plurality of bits, a histogram corresponding to the first plurality of bits; and modify, based on the first voltage threshold corresponding to the histogram, one or more of the first voltage threshold and the second voltage threshold, the voltage range bounded by the first voltage threshold and the second voltage threshold. ### Claim 12 (depends on 10) The system of claim 10, the controller further configured to: modify, based on the first voltage threshold and a second voltage threshold corresponding to a read operation of the first plurality of bits, one or more of the first voltage threshold and the second voltage threshold. ### Claim 13 (depends on 12) The system of claim 12, the controller further configured to: generate a magnitude of the LLR based on one or more of a voltage bounded by the voltage range, the second voltage threshold, the first plurality of bits, and the second plurality of bits. ### Claim 14 (depends on 12) The system of claim 12, the first voltage threshold corresponding to a first plurality of voltage thresholds, the second voltage threshold corresponding to a second plurality of voltage thresholds, and the voltage ranges corresponding to a plurality of voltage ranges between adjacent ones of the first plurality of voltage thresholds and the second plurality of voltage thresholds. ### Claim 15 (depends on 10) The system of claim 10, the controller further configured to: decode, based on the first plurality of bits and the second plurality of bits, the first plurality of bits by hard decoding; and modify the first voltage threshold, in response to an indication of failure corresponding to the decoding of the first plurality of bits by hard decoding. ### Claim 16 (depends on 10) The system of claim 10, the controller further configured to: generate, in response to an indication of failure corresponding to the decoding the first plurality of bits based on the LLR, a third voltage threshold corresponding to the read voltage for the first plurality of bits. ### Claim 17 (depends on 16) The system of claim 16, the controller further configured to: allocate, to a second voltage range bounded by the third voltage threshold, a log-likelihood ratio (LLR); and decode, based on the LLR corresponding to the second voltage range, the first plurality of bits. ### Claim 18 (depends on 16) The system of claim 16, the first voltage threshold corresponding to a first plurality of voltage thresholds, the third voltage threshold corresponding to a third plurality of voltage thresholds, and the voltage ranges corresponding to a plurality of voltage ranges between adjacent ones of the first plurality of voltage thresholds and the third plurality of voltage thresholds. ### Claim 19 A non-transitory computer readable medium including one or more instructions stored thereon and executable by a processor to: select, by a processor, a plurality of memory locations at a memory device, the memory locations corresponding to a first page including a first plurality of bits and a second page including a second plurality of bits; modify, by the processor and based on the first plurality of bits and the second plurality of bits, a first voltage threshold corresponding to a read voltage for the first plurality of bits; allocate, by the processor to a voltage range bounded by the first voltage threshold, a log-likelihood ratio (LLR); and decode, by the processor and based on the LLR corresponding to the voltage range, the first plurality of bits. ### Claim 20 (depends on 19) The computer readable medium of claim 19, wherein the computer readable medium further includes one or more instructions executable by the processor to: generate, by the processor and based on the first plurality of bits and the second plurality of bits, a histogram corresponding to the first plurality of bits; and modify, by the processor and based on the first voltage threshold corresponding to the histogram, one or more of the first voltage threshold and the second voltage threshold, the voltage range bounded by the first voltage threshold and the second voltage threshold.