# US 12,119,074 B2 · Data correction of redundant data storage

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- Number: US 12,119,074 B2
- Document ID: US12119074B2
- Status: Granted
- Kind: B2
- Application number: 17/955,439
- Filed: 2022-09-28
- Published: 2024-03-28
- Granted: 2024-10-15
- Earliest claimed: 2022-09-28
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Timothy Duryea
- Web page: https://patentgrep.com/patent/US12119074B2

## CPC

- G11C 7/24: Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 7/02: with means for avoiding parasitic signals
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 7/1039: {using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers}
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 2029/0411: {Online error correction}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

In one example, an apparatus comprises first, second and third memory devices, an error detection circuit, and an error correction circuit. The error detection circuit is configured to detect a mismatch among data stored at the first, second, and third memory devices, and responsive to detecting the mismatch, provide a correction signal representing a majority state of the data. The error correction circuit is configured to write the majority state of the data into at least one of the first, second, or third memory devices responsive to the correction signal.

## Claims

### Claim 1

An apparatus comprising:
a first memory device having a first data input and a first data output;
a second memory device having a second data input and a second data output;
a third memory device having a third data input and a third data output;
an error detection circuit having a first detection input, a second detection input, a third detection input, and a detection output, the first detection input coupled to the first data output, the second detection input coupled to the second data output, and the third detection input coupled to the third data output, the error detection circuit configured to:
detect a mismatch among data stored at the first, second, and third memory devices; and
responsive to detecting the mismatch, provide a correction signal at the detection output, the correction signal representing a majority state of the data; and
an error correction circuit having a correction input, a first correction output, a second correction output, and a third correction output, the correction input coupled to the detection output, the first correction output coupled to the first data input, the second correction output coupled to the second data input, the third correction output coupled to the third data input, and the error correction circuit configured to write the majority state of the data into at least one of the first, second, or third memory devices.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the data is first data, the error correction circuit has an external data input, and the error detection circuit is configured to provide a first data signal at the first, second, and third correction outputs to write second data to each of the first, second, and third memory devices responsive to a second data signal at the external data input.

### Claim 3 (depends on 1)

The apparatus of claim 1, further comprising a filter having a filter input and a filter output, the filter input coupled to the detection output, and the filter output coupled to the correction input.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the filter includes a resistor coupled between the filter input and the filter output, and a capacitor coupled to the filter output.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein the filter includes a buffer circuit coupled between the resistor and the filter output.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein the buffer circuit includes a Schmitt trigger circuit.

### Claim 7 (depends on 3)

The apparatus of claim 3, wherein the filter includes:
a sampling circuit having a sampling input and a sampling output, the sampling input coupled to the filter input, the sampling circuit configured to provide samples of a state of the filter input at the sampling output; and
a digital signal processor having a processing input coupled to the sampling output and a processing output coupled to the filter output, the digital processing circuit configured to generate the correction signal at the processing output based on averaging the samples.

### Claim 8 (depends on 1)

The apparatus of claim 1, further comprising a majority state determination circuit having first, second, and third candidate inputs and a majority output, the first candidate input coupled to the first data output, the second candidate input coupled to the second data output, and the third candidate input coupled to the third data output, the majority state determination circuit configured to set a state of the majority output responsive to a majority state of the first, second, and third candidate inputs.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein:
the first memory device includes a first sequential logic circuit having a first set input, a first reset input, a first non-inverting output, and a first inverting output, the first set and reset inputs coupled to the first data input, and the first non-inverting and inverting outputs coupled to the first data output;
the second memory device includes a second sequential logic circuit having a second set input, a second reset input, a second non-inverting output, and a second inverting output, the second set and reset inputs coupled to the second data input, and the second non-inverting and inverting outputs coupled to the second data output; and
the third memory device includes a third sequential logic circuit having a third set input, a third reset input, a third non-inverting output, and a third inverting output, the third set and reset inputs coupled to the third data input, and the third non-inverting and inverting outputs coupled to the third data output.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein each of the first, second, and third sequential logic circuits includes an R-S latch.

### Claim 11 (depends on 9)

The apparatus of claim 9, wherein:
the first sequential logic circuit includes a first flip-flop having a first clock terminal and a first reset terminal, the first clock terminal coupled to the first set input, and the first reset terminal coupled to the first reset input;
the second sequential logic circuit includes a second flip-flop having a second clock terminal and a second reset terminal, the second clock terminal coupled to the second set input, and the second reset terminal coupled to the second reset input; and
the third sequential logic circuit includes a third flip-flop having a third clock terminal and a third reset terminal, the third clock terminal coupled to the third set input, and the third reset terminal coupled to the third reset input.

### Claim 12 (depends on 9)

The apparatus of claim 9, wherein the error detection circuit includes:
a first error detection subcircuit having first detection sub-inputs and a first detection sub-output, the first detection sub-inputs coupled to the first inverting output, the second non-inverting output, and the third non-inverting output via the first detection input, and the first detection sub-output coupled to the detection output;
a second error detection subcircuit having second detection sub-inputs and a second detection sub-output, the second detection sub-inputs coupled to the first non-inverting output, the second inverting output, and the third inverting output via the first detection input, and the second detection sub-output coupled to the detection output;
a third error detection subcircuit having third detection sub-inputs and a third detection sub-output, the third detection sub-inputs coupled to the first non-inverting output, the second inverting output, and the third inverting output via the second detection input, and the third detection sub-output coupled to the detection output;
a fourth error detection subcircuit having fourth detection sub-inputs and a fourth detection sub-output, the fourth detection sub-inputs coupled to the first inverting output, the second non-inverting output, and the third inverting output via the second detection input, and the fourth detection sub-output coupled to the detection output;
a fifth error detection subcircuit having fifth detection sub-inputs and a fifth detection sub-output, the fifth detection sub-inputs coupled to the first non-inverting output, the second non-inverting output, and the third inverting output via the third detection input, and the fifth detection sub-output coupled to the detection output; and
a sixth error detection subcircuit having sixth detection sub-inputs and a sixth detection sub-output, the sixth detection sub-inputs coupled to the first inverting output, the second inverting output, and the third non-inverting output via the third detection input, and the sixth detection sub-output coupled to the detection output.

### Claim 13 (depends on 12)

The apparatus of claim 12, wherein each of the first through sixth error detection subcircuits includes an AND gate.

### Claim 14 (depends on 12)

The apparatus of claim 12, wherein the error correction circuit includes:
a first correction subcircuit having a first external data input, a first correction sub-input, and a first correction sub-output, the first correction sub-input coupled to the first detection sub-output via the correction input, and the first correction sub-output coupled to the first set input via the first correction output;
a second correction subcircuit having a second external data input, a second correction sub-input, and a second correction sub-output, the second correction sub-input coupled to the second detection sub-output via the correction input, and the second correction sub-output coupled to the first reset input via the first correction output;
a third correction subcircuit having a third external data input, a third correction sub-input, and a third correction sub-output, the third correction sub-input coupled to the third detection sub-output via the correction input, and the third correction sub-output coupled to the second set input via the second correction output;
a fourth correction subcircuit having a fourth external data input, a fourth correction sub-input, and a fourth correction sub-output, the fourth correction sub-input coupled to the fourth detection sub-output via the correction input, and the fourth correction sub-output coupled to the second reset input via the second correction output;
a fifth correction subcircuit having a fifth external data input, a fifth correction sub-input, and a fifth correction sub-output, the fifth correction sub-input coupled to the fifth detection sub-output via the correction input, and the fifth correction sub-output coupled to the third set input via the third correction output; and
a sixth correction subcircuit having a sixth external data input, a sixth correction sub-input, and a sixth correction sub-output, the sixth correction sub-input coupled to the sixth detection sub-output via the correction input, and the sixth correction sub-output coupled to the third reset input via the third correction output.

### Claim 15 (depends on 14)

The apparatus of claim 14, wherein each of the first through sixth correction subcircuit includes an OR gate or a NOR gate.

### Claim 16 (depends on 1)

The apparatus of claim 1, wherein each of the first, second, and third memory devices includes a random access memory (RAM) device.

### Claim 17 (depends on 1)

The apparatus of claim 1, wherein the error detection circuit is configured to detect the mismatch responsive to a change in a state of at least one of first, second, or third detection inputs.

### Claim 18 (depends on 1)

The apparatus of claim 1, wherein the error detection circuit is configured to, responsive to a clock signal:
determine a respective state of each of the first, second, and third detection inputs; and
detect the mismatch from the respective states.

### Claim 19

An apparatus comprising:
a first memory device configured to store a first copy of first data;
a second memory device configured to store a second copy of the first data;
a third memory device configured to store a third copy of the first data;
an instruction memory configured to store a set of instructions; and
a processor configured to execute the set of instructions to:
detect a mismatch between the first, second, and third copies of the first data stored at the respective first, second, and third memory devices;
generate a correction signal representing an uncorrupted state of the first data;
determine whether second data is received;
responsive to determining that the second data is received, store copies of the second data at the first, second, and third memory devices; and
responsive to determining that the second data is not received, provide the correction signal to at least one of the first, second, or third memory devices to write the uncorrupted state of the first data into at least one of the first, second, or third memory devices.

### Claim 20

A method comprising:
detecting a mismatch among copies of first data stored in a set of memory devices;
generating a correction signal representing an uncorrupted state of the first data;
determining whether second data is received;
responsive to determining that the second data is received, writing copies of the second data into the set of memory devices; and
responsive to determining that the second data is not received, providing the correction signal to at least one memory device of the set of memory devices to write the uncorrupted state of the first data into the at least one memory device.