# US 12,119,067 B2 · Comparison circuit and memory chip

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- Number: US 12,119,067 B2
- Document ID: US12119067B2
- Status: Granted
- Kind: B2
- Application number: 17/818,956
- Filed: 2022-08-10
- Published: 2022-12-01
- Granted: 2024-10-15
- Earliest claimed: 2020-12-16
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Lei Zhu; Jianyong Qin
- Web page: https://patentgrep.com/patent/US12119067B2

## CPC

- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G01R 31/31703: {Comparison aspects, e.g. signature analysis, comparators (concerning scan tests G01R31/318566; concerning testers G01R31/3193)}
- G11C 7/065: {Differential amplifiers of latching type}
- G11C 7/14: Dummy cell management; Sense reference voltage generators
- G11C 11/401: forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G11C 16/10: Programming or data input circuits
- G11C 16/32: Timing circuits
- H03K 19/21: EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A comparison circuit includes a comparison module, a state judgment module and a state storage module. The comparison module includes a first input end connected to a voltage to be measured and a second input end connected to a reference voltage. The state judgment module includes a first input end connected to a first output end of the comparison module and a second input end connected to a second output end of the comparison module. The state storage module includes an input end connected to the first output end of the comparison module and an enable end connected to an output end of the state judgment module. The embodiments of the disclosure may improve processing efficiency of the comparison circuit.

## Claims

### Claim 1

A comparison circuit, comprising:
a comparison module, comprising a first input end connected to a voltage to be measured and a second input end connected to a reference voltage;
a state judgment module, comprising a first input end connected to a first output end of the comparison module and a second input end connected to a second output end of the comparison module; and
a state storage module, comprising an input end connected to the first output end of the comparison module and an enable end connected to an output end of the state judgment module.

### Claim 2 (depends on 1)

The comparison circuit of claim 1, further comprising:
a pulse generation circuit, comprising an output end connected to an enable end of the comparison module.

### Claim 3 (depends on 2)

The comparison circuit of claim 2, wherein an input end of the pulse generation circuit receives a pulse enable signal, and a control end of the state storage module receives a storage control signal.

### Claim 4 (depends on 1)

The comparison circuit of claim 1, wherein the comparison module comprises:
a first transistor, comprising a gate serving as the first input end of the comparison module;
a second transistor, comprising a gate serving as the second input end of the comparison module;
a third transistor, comprising a source connected to a drain of the first transistor;
a fourth transistor, comprising a source connected to a drain of the second transistor;
a fifth transistor, comprising a drain serving as the first output end of the comparison module and connected to a drain of the third transistor and a gate of the fourth transistor, and a source connected to a power end;
a sixth transistor, comprising a drain serving as the second output end of the comparison module and connected to a drain of the fourth transistor and a gate of the third transistor, and a source connected to the power end; and
a seventh transistor, comprising a gate serving as the enable end of the comparison module, and a drain connected to a source of the first transistor and a source of the second transistor and a source grounded.

### Claim 5 (depends on 4)

The comparison circuit of claim 4, wherein the comparison module further comprises:
a first switching transistor, comprising a first end connected to the power end, a second end connected to the first output end of the comparison module, and a control end connected to the enable end of the comparison module; and
a second switching transistor, comprising a first end connected to the power end, a second end connected to the second output end of the comparison module, and a control end connected to the enable end of the comparison module.

### Claim 6 (depends on 5)

The comparison circuit of claim 5, wherein the comparison module further comprises:
a third switching transistor, comprising a first end connected to the power end, a second end connected to the drain of the first transistor, and a control end connected to the enable end of the comparison module; and
a fourth switching transistor, comprising a first end connected to the power end, a second end connected to the drain of the second transistor, and a control end connected to the enable end of the comparison module.

### Claim 7 (depends on 6)

The comparison circuit of claim 6, wherein the first switching transistor, the second switching transistor, the third switching transistor, and the fourth switching transistor are all P-type transistors.

### Claim 8 (depends on 6)

The comparison circuit of claim 6, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, and the seventh transistor are all N-type transistors.

### Claim 9 (depends on 6)

The comparison circuit of claim 6, wherein the fifth transistor and the sixth transistor are P-type transistors.

### Claim 10 (depends on 1)

The comparison circuit of claim 1, wherein the state storage module is a flip-flop or a register.

### Claim 11 (depends on 1)

The comparison circuit of claim 1, wherein the state judgment module comprises an exclusive OR gate.

### Claim 12 (depends on 1)

The comparison circuit of claim 1, wherein the voltage to be measured changes from a first voltage to a second voltage within time T.

### Claim 13 (depends on 12)

The comparison circuit of claim 12, wherein the reference voltage is greater than the first voltage and less than the second voltage.

### Claim 14 (depends on 1)

The comparison circuit of claim 1, wherein an output signal of the state judgment module is configured to control storage timing of the state storage module.

### Claim 15

A memory chip, comprising:
a comparison circuit, comprising:
a comparison module, comprising a first input end connected to a voltage to be measured and a second input end connected to a reference voltage;
a state judgment module, comprising a first input end connected to a first output end of the comparison module and a second input end connected to a second output end of the comparison module; and
a state storage module, comprising an input end connected to the first output end of the comparison module and an enable end connected to an output end of the state judgment module; and
a first power supply serving as the voltage to be measured, and a second power supply for supplying power to the comparison circuit.

### Claim 16 (depends on 15)

The memory chip of claim 15, further comprising:
a reference voltage generation circuit, configured to generate the reference voltage.